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chibios: Commit


Commit MetaInfo

Revisión14387 (tree)
Tiempo2021-05-17 21:44:07
Autorgdisirio

Log Message

STM32 USARTv2, USARTv3 updated for dynamic clocking.

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Diferencia incremental

--- trunk/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c (revision 14387)
@@ -228,8 +228,11 @@
228228 *
229229 * @param[in] sdp pointer to a @p SerialDriver object
230230 * @param[in] config the architecture-dependent serial driver configuration
231+ * @param[in] clock base clock for the USART
231232 */
232-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
233+static void usart_init(SerialDriver *sdp,
234+ const SerialConfig *config,
235+ uint32_t clock) {
233236 uint32_t brr;
234237 USART_TypeDef *u = sdp->usart;
235238
@@ -236,11 +239,11 @@
236239 /* Baud rate setting.*/
237240 #if STM32_SERIAL_USE_LPUART1
238241 if (sdp == &LPSD1) {
239- osalDbgAssert((sdp->clock >= config->speed * 3U) &&
240- (sdp->clock <= config->speed * 4096U),
242+ osalDbgAssert((clock >= config->speed * 3U) &&
243+ (clock <= config->speed * 4096U),
241244 "invalid baud rate vs input clock");
242245
243- brr = (uint32_t)(((uint64_t)sdp->clock * 256) / config->speed);
246+ brr = (uint32_t)(((uint64_t)clock * 256) / config->speed);
244247
245248 osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value");
246249 }
@@ -247,7 +250,7 @@
247250 else
248251 #endif
249252 {
250- brr = (uint32_t)(sdp->clock / config->speed);
253+ brr = (uint32_t)(clock / config->speed);
251254
252255 /* Correcting BRR value when oversampling by 8 instead of 16.
253256 Fraction is still 4 bits wide, but only lower 3 bits used.
@@ -602,7 +605,6 @@
602605 iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1);
603606 oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1);
604607 SD1.usart = USART1;
605- SD1.clock = STM32_USART1CLK;
606608 #if !defined(STM32_USART1_SUPPRESS_ISR) && defined(STM32_USART1_NUMBER)
607609 nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
608610 #endif
@@ -613,7 +615,6 @@
613615 iqObjectInit(&SD2.iqueue, sd_in_buf2, sizeof sd_in_buf2, NULL, &SD2);
614616 oqObjectInit(&SD2.oqueue, sd_out_buf2, sizeof sd_out_buf2, notify2, &SD2);
615617 SD2.usart = USART2;
616- SD2.clock = STM32_USART2CLK;
617618 #if !defined(STM32_USART2_SUPPRESS_ISR) && defined(STM32_USART2_NUMBER)
618619 nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
619620 #endif
@@ -624,7 +625,6 @@
624625 iqObjectInit(&SD3.iqueue, sd_in_buf3, sizeof sd_in_buf3, NULL, &SD3);
625626 oqObjectInit(&SD3.oqueue, sd_out_buf3, sizeof sd_out_buf3, notify3, &SD3);
626627 SD3.usart = USART3;
627- SD3.clock = STM32_USART3CLK;
628628 #if !defined(STM32_USART3_SUPPRESS_ISR) && defined(STM32_USART3_NUMBER)
629629 nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
630630 #endif
@@ -635,7 +635,6 @@
635635 iqObjectInit(&SD4.iqueue, sd_in_buf4, sizeof sd_in_buf4, NULL, &SD4);
636636 oqObjectInit(&SD4.oqueue, sd_out_buf4, sizeof sd_out_buf4, notify4, &SD4);
637637 SD4.usart = UART4;
638- SD4.clock = STM32_UART4CLK;
639638 #if !defined(STM32_UART4_SUPPRESS_ISR) && defined(STM32_UART4_NUMBER)
640639 nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
641640 #endif
@@ -646,7 +645,6 @@
646645 iqObjectInit(&SD5.iqueue, sd_in_buf5, sizeof sd_in_buf5, NULL, &SD5);
647646 oqObjectInit(&SD5.oqueue, sd_out_buf5, sizeof sd_out_buf5, notify5, &SD5);
648647 SD5.usart = UART5;
649- SD5.clock = STM32_UART5CLK;
650648 #if !defined(STM32_UART5_SUPPRESS_ISR) && defined(STM32_UART5_NUMBER)
651649 nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
652650 #endif
@@ -657,7 +655,6 @@
657655 iqObjectInit(&SD6.iqueue, sd_in_buf6, sizeof sd_in_buf6, NULL, &SD6);
658656 oqObjectInit(&SD6.oqueue, sd_out_buf6, sizeof sd_out_buf6, notify6, &SD6);
659657 SD6.usart = USART6;
660- SD6.clock = STM32_USART6CLK;
661658 #if !defined(STM32_USART6_SUPPRESS_ISR) && defined(STM32_USART6_NUMBER)
662659 nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
663660 #endif
@@ -668,7 +665,6 @@
668665 iqObjectInit(&SD7.iqueue, sd_in_buf7, sizeof sd_in_buf7, NULL, &SD7);
669666 oqObjectInit(&SD7.oqueue, sd_out_buf7, sizeof sd_out_buf7, notify7, &SD7);
670667 SD7.usart = UART7;
671- SD7.clock = STM32_UART7CLK;
672668 #if !defined(STM32_UART7_SUPPRESS_ISR) && defined(STM32_UART7_NUMBER)
673669 nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY);
674670 #endif
@@ -679,7 +675,6 @@
679675 iqObjectInit(&SD8.iqueue, sd_in_buf8, sizeof sd_in_buf8, NULL, &SD8);
680676 oqObjectInit(&SD8.oqueue, sd_out_buf8, sizeof sd_out_buf8, notify8, &SD8);
681677 SD8.usart = UART8;
682- SD8.clock = STM32_UART8CLK;
683678 #if !defined(STM32_UART8_SUPPRESS_ISR) && defined(STM32_UART8_NUMBER)
684679 nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY);
685680 #endif
@@ -690,7 +685,6 @@
690685 iqObjectInit(&LPSD1.iqueue, sd_in_buflp1, sizeof sd_in_buflp1, NULL, &LPSD1);
691686 oqObjectInit(&LPSD1.oqueue, sd_out_buflp1, sizeof sd_out_buflp1, notifylp1, &LPSD1);
692687 LPSD1.usart = LPUART1;
693- LPSD1.clock = STM32_LPUART1CLK;
694688 #if !defined(STM32_LPUART1_SUPPRESS_ISR) && defined(STM32_LPUART1_NUMBER)
695689 nvicEnableVector(STM32_LPUART1_NUMBER, STM32_SERIAL_LPUART1_PRIORITY);
696690 #endif
@@ -708,6 +702,7 @@
708702 * @notapi
709703 */
710704 void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
705+ uint32_t clock = 0U;
711706
712707 if (config == NULL)
713708 config = &default_config;
@@ -715,51 +710,60 @@
715710 if (sdp->state == SD_STOP) {
716711 #if STM32_SERIAL_USE_USART1
717712 if (&SD1 == sdp) {
713+ clock = STM32_USART1CLK;
718714 rccEnableUSART1(true);
719715 }
720716 #endif
721717 #if STM32_SERIAL_USE_USART2
722718 if (&SD2 == sdp) {
719+ clock = STM32_USART2CLK;
723720 rccEnableUSART2(true);
724721 }
725722 #endif
726723 #if STM32_SERIAL_USE_USART3
727724 if (&SD3 == sdp) {
725+ clock = STM32_USART3CLK;
728726 rccEnableUSART3(true);
729727 }
730728 #endif
731729 #if STM32_SERIAL_USE_UART4
732730 if (&SD4 == sdp) {
731+ clock = STM32_UART4CLK;
733732 rccEnableUART4(true);
734733 }
735734 #endif
736735 #if STM32_SERIAL_USE_UART5
737736 if (&SD5 == sdp) {
737+ clock = STM32_UART5CLK;
738738 rccEnableUART5(true);
739739 }
740740 #endif
741741 #if STM32_SERIAL_USE_USART6
742742 if (&SD6 == sdp) {
743+ clock = STM32_USART6CLK;
743744 rccEnableUSART6(true);
744745 }
745746 #endif
746747 #if STM32_SERIAL_USE_UART7
747748 if (&SD7 == sdp) {
749+ clock = STM32_UART7CLK;
748750 rccEnableUART7(true);
749751 }
750752 #endif
751753 #if STM32_SERIAL_USE_UART8
752754 if (&SD8 == sdp) {
755+ clock = STM32_UART8CLK;
753756 rccEnableUART8(true);
754757 }
755758 #endif
756759 #if STM32_SERIAL_USE_LPUART1
757760 if (&LPSD1 == sdp) {
761+ clock = STM32_LPUART1CLK;
758762 rccEnableLPUART1(true);
759763 }
760764 #endif
761765 }
762- usart_init(sdp, config);
766+ usart_init(sdp, config, clock);
763767 }
764768
765769 /**
--- trunk/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h (revision 14387)
@@ -542,8 +542,6 @@
542542 /* End of the mandatory fields.*/ \
543543 /* Pointer to the USART registers block.*/ \
544544 USART_TypeDef *usart; \
545- /* Clock frequency for the associated USART/UART.*/ \
546- uint32_t clock; \
547545 /* Mask to be applied on received frames.*/ \
548546 uint8_t rxmask;
549547
--- trunk/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.c (revision 14387)
@@ -185,8 +185,9 @@
185185 * @details This function must be invoked with interrupts disabled.
186186 *
187187 * @param[in] siop pointer to a @p SIODriver object
188+ * @param[in] clock base clock for the USART
188189 */
189-__STATIC_INLINE void usart_init(SIODriver *siop) {
190+__STATIC_INLINE void usart_init(SIODriver *siop, uint32_t clock) {
190191 USART_TypeDef *u = siop->usart;
191192 uint32_t presc, brr;
192193
@@ -197,11 +198,11 @@
197198 /* Baud rate setting.*/
198199 #if STM32_SIO_USE_LPUART1
199200 if (siop == &LPSIOD1) {
200- osalDbgAssert((siop->clock >= siop->config->baud * 3U) &&
201- (siop->clock <= siop->config->baud * 4096U),
201+ osalDbgAssert((clock >= siop->config->baud * 3U) &&
202+ (clock <= siop->config->baud * 4096U),
202203 "invalid baud rate vs input clock");
203204
204- brr = (uint32_t)(((uint64_t)(siop->clock / presc) * (uint64_t)256) / siop->config->baud);
205+ brr = (uint32_t)(((uint64_t)(clock / presc) * (uint64_t)256) / siop->config->baud);
205206
206207 osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value");
207208 }
@@ -208,7 +209,7 @@
208209 else
209210 #endif
210211 {
211- brr = (uint32_t)((siop->clock / presc) / siop->config->baud);
212+ brr = (uint32_t)((clock / presc) / siop->config->baud);
212213
213214 /* Correcting BRR value when oversampling by 8 instead of 16.
214215 Fraction is still 4 bits wide, but only lower 3 bits used.
@@ -246,47 +247,38 @@
246247 #if STM32_SIO_USE_USART1 == TRUE
247248 sioObjectInit(&SIOD1);
248249 SIOD1.usart = USART1;
249- SIOD1.clock = STM32_USART1CLK;
250250 #endif
251251 #if STM32_SIO_USE_USART2 == TRUE
252252 sioObjectInit(&SIOD2);
253253 SIOD2.usart = USART2;
254- SIOD2.clock = STM32_USART2CLK;
255254 #endif
256255 #if STM32_SIO_USE_USART3 == TRUE
257256 sioObjectInit(&SIOD3);
258257 SIOD3.usart = USART3;
259- SIOD3.clock = STM32_USART3CLK;
260258 #endif
261259 #if STM32_SIO_USE_UART4 == TRUE
262260 sioObjectInit(&SIOD4);
263261 SIOD4.usart = UART4;
264- SIOD4.clock = STM32_UART4CLK;
265262 #endif
266263 #if STM32_SIO_USE_UART5 == TRUE
267264 sioObjectInit(&SIOD5);
268265 SIOD5.usart = UART5;
269- SIOD5.clock = STM32_UART5CLK;
270266 #endif
271267 #if STM32_SIO_USE_USART6 == TRUE
272268 sioObjectInit(&SIOD6);
273269 SIOD6.usart = USART6;
274- SIOD6.clock = STM32_USART6CLK;
275270 #endif
276271 #if STM32_SIO_USE_UART7 == TRUE
277272 sioObjectInit(&SIOD7);
278273 SIOD7.usart = UART7;
279- SIOD7.clock = STM32_UART7CLK;
280274 #endif
281275 #if STM32_SIO_USE_UART8 == TRUE
282276 sioObjectInit(&SIOD8);
283277 SIOD8.usart = UART8;
284- SIOD8.clock = STM32_UART8CLK;
285278 #endif
286279 #if STM32_SIO_USE_LPUART1 == TRUE
287280 sioObjectInit(&LPSIOD1);
288281 LPSIOD1.usart = LPUART1;
289- LPSIOD1.clock = STM32_LPUART1CLK;
290282 #endif
291283
292284 }
@@ -302,6 +294,7 @@
302294 * @notapi
303295 */
304296 bool sio_lld_start(SIODriver *siop) {
297+ uint32_t clock = 0U;
305298
306299 /* Using the default configuration if the application passed a
307300 NULL pointer.*/
@@ -316,6 +309,7 @@
316309 }
317310 #if STM32_SIO_USE_USART1 == TRUE
318311 else if (&SIOD1 == siop) {
312+ clock = STM32_USART1CLK;
319313 rccResetUSART1();
320314 rccEnableUSART1(true);
321315 }
@@ -322,6 +316,7 @@
322316 #endif
323317 #if STM32_SIO_USE_USART2 == TRUE
324318 else if (&SIOD2 == siop) {
319+ clock = STM32_USART2CLK;
325320 rccResetUSART2();
326321 rccEnableUSART2(true);
327322 }
@@ -328,6 +323,7 @@
328323 #endif
329324 #if STM32_SIO_USE_USART3 == TRUE
330325 else if (&SIOD3 == siop) {
326+ clock = STM32_USART3CLK;
331327 rccResetUSART3();
332328 rccEnableUSART3(true);
333329 }
@@ -334,6 +330,7 @@
334330 #endif
335331 #if STM32_SIO_USE_UART4 == TRUE
336332 else if (&SIOD4 == siop) {
333+ clock = STM32_UART4CLK;
337334 rccResetUART4();
338335 rccEnableUART4(true);
339336 }
@@ -340,6 +337,7 @@
340337 #endif
341338 #if STM32_SIO_USE_UART5 == TRUE
342339 else if (&SIOD5 == siop) {
340+ clock = STM32_UART5CLK;
343341 rccResetUART5();
344342 rccEnableUART5(true);
345343 }
@@ -346,6 +344,7 @@
346344 #endif
347345 #if STM32_SIO_USE_USART6 == TRUE
348346 else if (&SIOD6 == siop) {
347+ clock = STM32_USART6CLK;
349348 rccResetUSART6();
350349 rccEnableUSART6(true);
351350 }
@@ -352,6 +351,7 @@
352351 #endif
353352 #if STM32_SIO_USE_UART7 == TRUE
354353 else if (&SIOD7 == siop) {
354+ clock = STM32_UART7CLK;
355355 rccResetUART7();
356356 rccEnableUART7(true);
357357 }
@@ -358,6 +358,7 @@
358358 #endif
359359 #if STM32_SIO_USE_UART8 == TRUE
360360 else if (&SIOD8 == siop) {
361+ clock = STM32_UART8CLK;
361362 rccResetUART8();
362363 rccEnableUART8(true);
363364 }
@@ -364,6 +365,7 @@
364365 #endif
365366 #if STM32_SIO_USE_LPUART1 == TRUE
366367 else if (&LPSIOD1 == siop) {
368+ clock = STM32_LPUART1CLK;
367369 rccResetLPUART1();
368370 rccEnableLPUART1(true);
369371 }
@@ -382,7 +384,7 @@
382384 }
383385
384386 /* Configures the peripheral.*/
385- usart_init(siop);
387+ usart_init(siop, clock);
386388
387389 return false;
388390 }
--- trunk/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.h (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv2/hal_sio_lld.h (revision 14387)
@@ -262,9 +262,7 @@
262262 */
263263 #define sio_lld_driver_fields \
264264 /* Pointer to the USARTx registers block.*/ \
265- USART_TypeDef *usart; \
266- /* USART clock frequency.*/ \
267- uint32_t clock
265+ USART_TypeDef *usart
268266
269267 /**
270268 * @brief Low level fields of the SIO configuration structure.
--- trunk/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c (revision 14387)
@@ -250,8 +250,9 @@
250250 * @details This function must be invoked with interrupts disabled.
251251 *
252252 * @param[in] uartp pointer to the @p UARTDriver object
253+ * @param[in] clock base clock for the USART
253254 */
254-static void usart_start(UARTDriver *uartp) {
255+static void usart_start(UARTDriver *uartp, uint32_t clock) {
255256 uint32_t fck;
256257 uint32_t cr1;
257258 const uint32_t tmo = uartp->config->timeout;
@@ -261,7 +262,7 @@
261262 usart_stop(uartp);
262263
263264 /* Baud rate setting.*/
264- fck = (uint32_t)(uartp->clock / uartp->config->speed);
265+ fck = (uint32_t)(clock / uartp->config->speed);
265266
266267 /* Correcting USARTDIV when oversampling by 8 instead of 16.
267268 Fraction is still 4 bits wide, but only lower 3 bits used.
@@ -534,7 +535,6 @@
534535 #if STM32_UART_USE_USART1
535536 uartObjectInit(&UARTD1);
536537 UARTD1.usart = USART1;
537- UARTD1.clock = STM32_USART1CLK;
538538 UARTD1.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
539539 UARTD1.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
540540 UARTD1.dmarx = NULL;
@@ -547,7 +547,6 @@
547547 #if STM32_UART_USE_USART2
548548 uartObjectInit(&UARTD2);
549549 UARTD2.usart = USART2;
550- UARTD2.clock = STM32_USART2CLK;
551550 UARTD2.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
552551 UARTD2.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
553552 UARTD2.dmarx = NULL;
@@ -560,7 +559,6 @@
560559 #if STM32_UART_USE_USART3
561560 uartObjectInit(&UARTD3);
562561 UARTD3.usart = USART3;
563- UARTD3.clock = STM32_USART3CLK;
564562 UARTD3.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
565563 UARTD3.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
566564 UARTD3.dmarx = NULL;
@@ -573,7 +571,6 @@
573571 #if STM32_UART_USE_UART4
574572 uartObjectInit(&UARTD4);
575573 UARTD4.usart = UART4;
576- UARTD4.clock = STM32_UART4CLK;
577574 UARTD4.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
578575 UARTD4.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
579576 UARTD4.dmarx = NULL;
@@ -586,7 +583,6 @@
586583 #if STM32_UART_USE_UART5
587584 uartObjectInit(&UARTD5);
588585 UARTD5.usart = UART5;
589- UARTD5.clock = STM32_UART5CLK;
590586 UARTD5.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
591587 UARTD5.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
592588 UARTD5.dmarx = NULL;
@@ -599,7 +595,6 @@
599595 #if STM32_UART_USE_USART6
600596 uartObjectInit(&UARTD6);
601597 UARTD6.usart = USART6;
602- UARTD6.clock = STM32_USART6CLK;
603598 UARTD6.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
604599 UARTD6.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
605600 UARTD6.dmarx = NULL;
@@ -612,7 +607,6 @@
612607 #if STM32_UART_USE_UART7
613608 uartObjectInit(&UARTD7);
614609 UARTD7.usart = UART7;
615- UARTD7.clock = STM32_UART7CLK;
616610 UARTD7.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
617611 UARTD7.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
618612 UARTD7.dmarx = NULL;
@@ -625,7 +619,6 @@
625619 #if STM32_UART_USE_UART8
626620 uartObjectInit(&UARTD8);
627621 UARTD8.usart = UART8;
628- UARTD8.clock = STM32_UART8CLK;
629622 UARTD8.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
630623 UARTD8.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
631624 UARTD8.dmarx = NULL;
@@ -644,10 +637,15 @@
644637 * @notapi
645638 */
646639 void uart_lld_start(UARTDriver *uartp) {
640+ uint32_t clock = 0U;
647641
648642 if (uartp->state == UART_STOP) {
643+
644+ if (false) {
645+ }
649646 #if STM32_UART_USE_USART1
650- if (&UARTD1 == uartp) {
647+ else if (&UARTD1 == uartp) {
648+ clock = STM32_USART1CLK;
651649 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART1_RX_DMA_STREAM,
652650 STM32_UART_USART1_IRQ_PRIORITY,
653651 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -672,7 +670,8 @@
672670 #endif
673671
674672 #if STM32_UART_USE_USART2
675- if (&UARTD2 == uartp) {
673+ else if (&UARTD2 == uartp) {
674+ clock = STM32_USART2CLK;
676675 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART2_RX_DMA_STREAM,
677676 STM32_UART_USART2_IRQ_PRIORITY,
678677 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -697,7 +696,8 @@
697696 #endif
698697
699698 #if STM32_UART_USE_USART3
700- if (&UARTD3 == uartp) {
699+ else if (&UARTD3 == uartp) {
700+ clock = STM32_USART3CLK;
701701 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART3_RX_DMA_STREAM,
702702 STM32_UART_USART3_IRQ_PRIORITY,
703703 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -722,7 +722,8 @@
722722 #endif
723723
724724 #if STM32_UART_USE_UART4
725- if (&UARTD4 == uartp) {
725+ else if (&UARTD4 == uartp) {
726+ clock = STM32_UART4CLK;
726727 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART4_RX_DMA_STREAM,
727728 STM32_UART_UART4_IRQ_PRIORITY,
728729 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -747,7 +748,8 @@
747748 #endif
748749
749750 #if STM32_UART_USE_UART5
750- if (&UARTD5 == uartp) {
751+ else if (&UARTD5 == uartp) {
752+ clock = STM32_UART5CLK;
751753 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART5_RX_DMA_STREAM,
752754 STM32_UART_UART5_IRQ_PRIORITY,
753755 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -772,7 +774,8 @@
772774 #endif
773775
774776 #if STM32_UART_USE_USART6
775- if (&UARTD6 == uartp) {
777+ else if (&UARTD6 == uartp) {
778+ clock = STM32_USART6CLK;
776779 uartp->dmarx = dmaStreamAllocI(STM32_UART_USART6_RX_DMA_STREAM,
777780 STM32_UART_USART6_IRQ_PRIORITY,
778781 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -797,7 +800,8 @@
797800 #endif
798801
799802 #if STM32_UART_USE_UART7
800- if (&UARTD7 == uartp) {
803+ else if (&UARTD7 == uartp) {
804+ clock = STM32_UART7CLK;
801805 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART7_RX_DMA_STREAM,
802806 STM32_UART_UART7_IRQ_PRIORITY,
803807 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -822,7 +826,8 @@
822826 #endif
823827
824828 #if STM32_UART_USE_UART8
825- if (&UARTD8 == uartp) {
829+ else if (&UARTD8 == uartp) {
830+ clock = STM32_UART8CLK;
826831 uartp->dmarx = dmaStreamAllocI(STM32_UART_UART8_RX_DMA_STREAM,
827832 STM32_UART_UART8_IRQ_PRIORITY,
828833 (stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
@@ -845,6 +850,9 @@
845850 #endif
846851 }
847852 #endif
853+ else {
854+ osalDbgAssert(false, "invalid USART instance");
855+ }
848856
849857 /* Static DMA setup, the transfer size depends on the USART settings,
850858 it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
@@ -859,7 +867,7 @@
859867
860868 uartp->rxstate = UART_RX_IDLE;
861869 uartp->txstate = UART_TX_IDLE;
862- usart_start(uartp);
870+ usart_start(uartp, clock);
863871 }
864872
865873 /**
--- trunk/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h (revision 14387)
@@ -820,10 +820,6 @@
820820 */
821821 USART_TypeDef *usart;
822822 /**
823- * @brief Clock frequency for the associated USART/UART.
824- */
825- uint32_t clock;
826- /**
827823 * @brief Receive DMA mode bit mask.
828824 */
829825 uint32_t dmarxmode;
--- trunk/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.c (revision 14387)
@@ -193,8 +193,9 @@
193193 * @details This function must be invoked with interrupts disabled.
194194 *
195195 * @param[in] siop pointer to a @p SIODriver object
196+ * @param[in] clock base clock for the USART
196197 */
197-__STATIC_INLINE void usart_init(SIODriver *siop) {
198+__STATIC_INLINE void usart_init(SIODriver *siop, uint32_t clock) {
198199 USART_TypeDef *u = siop->usart;
199200 uint32_t presc, brr;
200201
@@ -205,11 +206,11 @@
205206 /* Baud rate setting.*/
206207 #if STM32_SIO_USE_LPUART1
207208 if (siop == &LPSIOD1) {
208- osalDbgAssert((siop->clock >= siop->config->baud * 3U) &&
209- (siop->clock <= siop->config->baud * 4096U),
209+ osalDbgAssert((clock >= siop->config->baud * 3U) &&
210+ (clock <= siop->config->baud * 4096U),
210211 "invalid baud rate vs input clock");
211212
212- brr = (uint32_t)(((uint64_t)(siop->clock / presc) * (uint64_t)256) / siop->config->baud);
213+ brr = (uint32_t)(((uint64_t)(clock / presc) * (uint64_t)256) / siop->config->baud);
213214
214215 osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value");
215216 }
@@ -216,7 +217,7 @@
216217 else
217218 #endif
218219 {
219- brr = (uint32_t)((siop->clock / presc) / siop->config->baud);
220+ brr = (uint32_t)((clock / presc) / siop->config->baud);
220221
221222 /* Correcting BRR value when oversampling by 8 instead of 16.
222223 Fraction is still 4 bits wide, but only lower 3 bits used.
@@ -255,49 +256,39 @@
255256 #if STM32_SIO_USE_USART1 == TRUE
256257 sioObjectInit(&SIOD1);
257258 SIOD1.usart = USART1;
258- SIOD1.clock = STM32_USART1CLK;
259259 #endif
260260 #if STM32_SIO_USE_USART2 == TRUE
261261 sioObjectInit(&SIOD2);
262262 SIOD2.usart = USART2;
263- SIOD2.clock = STM32_USART2CLK;
264263 #endif
265264 #if STM32_SIO_USE_USART3 == TRUE
266265 sioObjectInit(&SIOD3);
267266 SIOD3.usart = USART3;
268- SIOD3.clock = STM32_USART3CLK;
269267 #endif
270268 #if STM32_SIO_USE_UART4 == TRUE
271269 sioObjectInit(&SIOD4);
272270 SIOD4.usart = UART4;
273- SIOD4.clock = STM32_UART4CLK;
274271 #endif
275272 #if STM32_SIO_USE_UART5 == TRUE
276273 sioObjectInit(&SIOD5);
277274 SIOD5.usart = UART5;
278- SIOD5.clock = STM32_UART5CLK;
279275 #endif
280276 #if STM32_SIO_USE_USART6 == TRUE
281277 sioObjectInit(&SIOD6);
282278 SIOD6.usart = USART6;
283- SIOD6.clock = STM32_USART6CLK;
284279 #endif
285280 #if STM32_SIO_USE_UART7 == TRUE
286281 sioObjectInit(&SIOD7);
287282 SIOD7.usart = UART7;
288- SIOD7.clock = STM32_UART7CLK;
289283 #endif
290284 #if STM32_SIO_USE_UART8 == TRUE
291285 sioObjectInit(&SIOD8);
292286 SIOD8.usart = UART8;
293- SIOD8.clock = STM32_UART8CLK;
294287 #endif
295288 #if STM32_SIO_USE_LPUART1 == TRUE
296289 sioObjectInit(&LPSIOD1);
297290 LPSIOD1.usart = LPUART1;
298- LPSIOD1.clock = STM32_LPUART1CLK;
299291 #endif
300-
301292 }
302293
303294 /**
@@ -311,6 +302,7 @@
311302 * @notapi
312303 */
313304 bool sio_lld_start(SIODriver *siop) {
305+ uint32_t clock = 0U;
314306
315307 /* Using the default configuration if the application passed a
316308 NULL pointer.*/
@@ -325,6 +317,7 @@
325317 }
326318 #if STM32_SIO_USE_USART1 == TRUE
327319 else if (&SIOD1 == siop) {
320+ clock = STM32_USART1CLK;
328321 rccResetUSART1();
329322 rccEnableUSART1(true);
330323 }
@@ -331,6 +324,7 @@
331324 #endif
332325 #if STM32_SIO_USE_USART2 == TRUE
333326 else if (&SIOD2 == siop) {
327+ clock = STM32_USART2CLK;
334328 rccResetUSART2();
335329 rccEnableUSART2(true);
336330 }
@@ -337,6 +331,7 @@
337331 #endif
338332 #if STM32_SIO_USE_USART3 == TRUE
339333 else if (&SIOD3 == siop) {
334+ clock = STM32_USART3CLK;
340335 rccResetUSART3();
341336 rccEnableUSART3(true);
342337 }
@@ -343,6 +338,7 @@
343338 #endif
344339 #if STM32_SIO_USE_UART4 == TRUE
345340 else if (&SIOD4 == siop) {
341+ clock = STM32_UART4CLK;
346342 rccResetUART4();
347343 rccEnableUART4(true);
348344 }
@@ -349,6 +345,7 @@
349345 #endif
350346 #if STM32_SIO_USE_UART5 == TRUE
351347 else if (&SIOD5 == siop) {
348+ clock = STM32_UART5CLK;
352349 rccResetUART5();
353350 rccEnableUART5(true);
354351 }
@@ -355,6 +352,7 @@
355352 #endif
356353 #if STM32_SIO_USE_USART6 == TRUE
357354 else if (&SIOD6 == siop) {
355+ clock = STM32_USART6CLK;
358356 rccResetUSART6();
359357 rccEnableUSART6(true);
360358 }
@@ -361,6 +359,7 @@
361359 #endif
362360 #if STM32_SIO_USE_UART7 == TRUE
363361 else if (&SIOD7 == siop) {
362+ clock = STM32_UART7CLK;
364363 rccResetUART7();
365364 rccEnableUART7(true);
366365 }
@@ -367,6 +366,7 @@
367366 #endif
368367 #if STM32_SIO_USE_UART8 == TRUE
369368 else if (&SIOD8 == siop) {
369+ clock = STM32_UART8CLK;
370370 rccResetUART8();
371371 rccEnableUART8(true);
372372 }
@@ -373,6 +373,7 @@
373373 #endif
374374 #if STM32_SIO_USE_LPUART1 == TRUE
375375 else if (&LPSIOD1 == siop) {
376+ clock = STM32_LPUART1CLK;
376377 rccResetLPUART1();
377378 rccEnableLPUART1(true);
378379 }
@@ -391,7 +392,7 @@
391392 }
392393
393394 /* Configures the peripheral.*/
394- usart_init(siop);
395+ usart_init(siop, clock);
395396
396397 return false;
397398 }
--- trunk/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h (revision 14386)
+++ trunk/os/hal/ports/STM32/LLD/USARTv3/hal_sio_lld.h (revision 14387)
@@ -38,7 +38,7 @@
3838 /*===========================================================================*/
3939
4040 /**
41- * @name PLATFORM configuration options
41+ * @name STM32 configuration options
4242 * @{
4343 */
4444 /**
@@ -266,9 +266,7 @@
266266 */
267267 #define sio_lld_driver_fields \
268268 /* Pointer to the USARTx registers block.*/ \
269- USART_TypeDef *usart; \
270- /* USART clock frequency.*/ \
271- uint32_t clock
269+ USART_TypeDef *usart
272270
273271 /**
274272 * @brief Low level fields of the SIO configuration structure.
--- trunk/readme.txt (revision 14386)
+++ trunk/readme.txt (revision 14387)
@@ -74,6 +74,7 @@
7474 *****************************************************************************
7575
7676 *** Next ***
77+- NEW: USARTv2, USARTv3 updated for dynamic clocking.
7778 - NEW: Dynamic support implemented for STM32G4xx.
7879 - NEW: Dynamic clocks support in HAL.
7980 - NEW: Reload feature added to RT virtual timers.
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