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mcuhal.arm: Commit

самопильный ХАЛ над библиотекой milandr SPL. позиционируется наличие порта порт на STM32 SPL.


Commit MetaInfo

Revisión75d7d69b7927965146a41c5206def68d67615a16 (tree)
Tiempo2022-06-02 07:32:10
Autoralexrayne <alexraynepe196@gmai...>
Commiteralexrayne

Log Message

+mcu ra2l: hal_uart - basic uart HAL implementation over R_SCI_UART
+hal_uart: UART_rx_head/tail, UART_tx_busy
!mcu ra2l: r_sci_uartx: R_SCI_UART_tx_busy - fixed for curretn FSP R_SCI_UART DTC mode

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Diferencia incremental

diff -r 3a7f1912be1c -r 75d7d69b7927 cpu/renesas/ra2l.fsp/dev/hal_uart.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cpu/renesas/ra2l.fsp/dev/hal_uart.c Thu Jun 02 01:32:10 2022 +0300
@@ -0,0 +1,162 @@
1+/*
2+ * hal_uart.c
3+ *
4+ * Created on: 28/04/2022
5+ * Author: <alexraynepe196@gmail.com>
6+ * ----------------------------------------------------------------------
7+ Copyright (c) alexrayne
8+
9+ All rights reserved.
10+ Redistribution and use in source and binary forms, with or without
11+ modification, are permitted provided that the following conditions are met:
12+ - Redistributions of source code must retain the above copyright
13+ notice, this list of conditions and the following disclaimer.
14+ - Redistributions in binary form must reproduce the above copyright
15+ notice, this list of conditions and the following disclaimer in the
16+ documentation and/or other materials provided with the distribution.
17+ - Neither the name of ARM nor the names of its contributors may be used
18+ to endorse or promote products derived from this software without
19+ specific prior written permission.
20+ *
21+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31+ POSSIBILITY OF SUCH DAMAGE. *
32+ * ----------------------------------------------------------------------
33+ * Renesas implementation of HAL UART for proto-threads
34+ */
35+
36+#include "hal_uart.h"
37+#include "r_sci_uart.h"
38+
39+
40+
41+void UART_rsci_handle(uart_callback_args_t *arg){
42+ UART_Device* uart = (UART_Device*)arg->p_context;
43+
44+ if ( arg->event & (UART_EVENT_RX_ANY | UART_EVENT_ERR_ANY) )
45+ if (uart->rx_ctx){
46+ process_poll( (struct process *)(uart->rx_ctx) );
47+ }
48+
49+ if ( arg->event & UART_EVENT_TX_ANY)
50+ if (uart->tx_ctx){
51+ process_poll( (struct process *)(uart->tx_ctx) );
52+ }
53+
54+ if (uart->iohandle) {
55+ int ev = arg->event | (arg->data << 8);
56+ (uart->iohandle)(ev, uart);
57+ }
58+}
59+
60+UARTError UART_init(UART_Device* uart, uart_ctrl_t* port){
61+ uart->port = port;
62+
63+#if SCI_UART_CFG_DTC_SUPPORTED
64+ sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) port;
65+ transfer_instance_t const * drdma = p_ctrl->p_cfg->p_transfer_rx;
66+ if ( drdma != NULL )
67+ uart->rx_dma = drdma->p_cfg->p_info;
68+ else
69+ uart->rx_dma = NULL;
70+#else
71+ uart->rx_dma = NULL;
72+#endif
73+
74+ uart->rx_ctx = NULL;
75+ uart->tx_ctx = NULL;
76+
77+ return R_SCI_UART_CallbackSet(uart->port, (UART_rsci_handle), uart, NULL);
78+}
79+
80+
81+UARTError UART_read(UART_Device* uart, void* p_dest, unsigned bytes){
82+ uart->rx_ctx = PROCESS_CURRENT();
83+ return R_SCI_UART_Read(uart->port, (uint8_t*)p_dest, bytes);
84+}
85+
86+UARTError UART_write(UART_Device* uart, const void* p_src, unsigned bytes){
87+ uart->tx_ctx = PROCESS_CURRENT();
88+ return R_SCI_UART_Write(uart->port, (const uint8_t*) p_src, bytes);
89+}
90+
91+/// @brief check that R_SCI_UART_Write buffers empty and io sending inactive
92+bool UART_flush(UART_Device* uart){
93+ if ( !UART_tx_busy(uart) ){
94+ sci_uart_instance_ctrl_t* self = (sci_uart_instance_ctrl_t*)(uart->port);
95+ return ( ( UART_GetFlagStatus( self->p_reg ) & UART_FLAG_TXC) != 0 );
96+ }
97+ return false;
98+}
99+
100+
101+
102+
103+
104+
105+/// @brief check that R_SCI_UART_Write active
106+bool R_SCI_UART_tx_busy(uart_ctrl_t * p_api_ctrl){
107+ sci_uart_instance_ctrl_t* self = (sci_uart_instance_ctrl_t*)p_api_ctrl;
108+ return __HAL_USART_GET_IT( self->p_reg, (USART_IT_TX | USART_IT_TC) ) != 0;
109+}
110+
111+
112+/// @brief receive data pointer
113+/// @return != NULL - pointer to receiver buffer head
114+/// == NULL - read not active
115+uint8_t* R_SCI_UART_rx_tail(uart_ctrl_t * const p_api_ctrl){
116+ sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl;
117+
118+#if SCI_UART_CFG_DTC_SUPPORTED
119+ transfer_instance_t const * drdma = p_ctrl->p_cfg->p_transfer_rx;
120+ if ( drdma != NULL ){
121+ transfer_info_t * rx_dma = drdma->p_cfg->p_info;
122+ if (rx_dma->length > 0)
123+ return rx_dma->p_dest;
124+ return NULL;
125+ }
126+#endif
127+
128+ if (p_ctrl->rx_dest_bytes > 0){
129+ return (uint8_t*)p_ctrl->p_rx_dest;
130+ }
131+
132+ return NULL;
133+}
134+
135+
136+#if SCI_UART_CFG_DTC_SUPPORTED
137+uint8_t* R_SCI_UART_rx_head(uart_ctrl_t * const p_api_ctrl){
138+ sci_uart_instance_ctrl_t * p_ctrl = (sci_uart_instance_ctrl_t *) p_api_ctrl;
139+ return (uint8_t*)(p_ctrl->p_rx_dest);
140+}
141+#endif
142+
143+
144+/// @brief receive data pointer
145+/// @return != NULL - pointer to receiver buffer head
146+/// == NULL - read not active
147+uint8_t* UART_rx_tail(UART_Device* uart){
148+ transfer_info_t* rx_dma = (transfer_info_t*)uart->rx_dma;
149+ if (rx_dma != NULL){
150+ if (rx_dma->length > 0)
151+ return rx_dma->p_dest;
152+ return NULL;
153+ }
154+ else {
155+ sci_uart_instance_ctrl_t* self = (sci_uart_instance_ctrl_t*)(uart->port);
156+ if (self->rx_dest_bytes > 0){
157+ return (uint8_t*)self->p_rx_dest;
158+ }
159+ return NULL;
160+ }
161+
162+}
diff -r 3a7f1912be1c -r 75d7d69b7927 cpu/renesas/ra2l.fsp/dev/hal_uart.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cpu/renesas/ra2l.fsp/dev/hal_uart.h Thu Jun 02 01:32:10 2022 +0300
@@ -0,0 +1,154 @@
1+/*
2+ * hal_uart.h
3+ *
4+ * Created on: 28/04/2022
5+ * Author: <alexraynepe196@gmail.com>
6+ * ----------------------------------------------------------------------
7+ Copyright (c) alexrayne
8+
9+ All rights reserved.
10+ Redistribution and use in source and binary forms, with or without
11+ modification, are permitted provided that the following conditions are met:
12+ - Redistributions of source code must retain the above copyright
13+ notice, this list of conditions and the following disclaimer.
14+ - Redistributions in binary form must reproduce the above copyright
15+ notice, this list of conditions and the following disclaimer in the
16+ documentation and/or other materials provided with the distribution.
17+ - Neither the name of ARM nor the names of its contributors may be used
18+ to endorse or promote products derived from this software without
19+ specific prior written permission.
20+ *
21+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31+ POSSIBILITY OF SUCH DAMAGE. *
32+ * ----------------------------------------------------------------------
33+ * Renesas implementation of HAL UART for proto-threads
34+ */
35+
36+#ifndef BSP_CPU_DEV_HAL_UART_H_
37+#define BSP_CPU_DEV_HAL_UART_H_
38+
39+//#include <halos_types.h>
40+#include "r_sci_uartx.h"
41+#include <mcu_usart.h>
42+#include <OsProcess.h>
43+
44+
45+
46+//============================================================================================
47+
48+// TODO: migrate -> DevResult
49+typedef fsp_err_t UARTError;
50+enum {
51+ UARTERR_OK = 0,
52+};
53+
54+
55+
56+//============================================================================================
57+
58+enum {
59+ /* uart_event_t :
60+ UART_EVENT_RX_COMPLETE , // = (1UL << 0), ///< Receive complete event
61+ UART_EVENT_TX_COMPLETE , // = (1UL << 1), ///< Transmit complete event
62+ UART_EVENT_RX_CHAR , // = (1UL << 2), ///< Character received
63+ UART_EVENT_ERR_PARITY , // = (1UL << 3), ///< Parity error event
64+ UART_EVENT_ERR_FRAMING , // = (1UL << 4), ///< Mode fault error event
65+ UART_EVENT_ERR_OVERFLOW , // = (1UL << 5), ///< FIFO Overflow error event
66+ UART_EVENT_BREAK_DETECT , // = (1UL << 6), ///< Break detect error event
67+ UART_EVENT_TX_DATA_EMPTY , // = (1UL << 7), ///< Last byte is transmitting, ready for more data
68+*/
69+ UART_EVENT_ERR_ANY = UART_EVENT_ERR_PARITY
70+ | UART_EVENT_ERR_FRAMING
71+ | UART_EVENT_ERR_OVERFLOW
72+ | UART_EVENT_BREAK_DETECT
73+ ,
74+ UART_EVENT_TX_ANY = UART_EVENT_TX_DATA_EMPTY | UART_EVENT_TX_COMPLETE,
75+ UART_EVENT_RX_ANY = UART_EVENT_RX_CHAR | UART_EVENT_RX_COMPLETE,
76+};
77+
78+// @sa @sa uart_event_t
79+typedef int UARTIOEvent;
80+
81+typedef void (* UARTEventHandle)(UARTIOEvent event, void const* p_context);
82+
83+typedef struct UART_Device{
84+ uart_ctrl_t* port;
85+
86+ //process context for io ISR wake
87+ void* tx_ctx;
88+ void* rx_ctx;
89+
90+ void* rx_dma; /* transfer_info_t* */
91+
92+
93+ UARTEventHandle iohandle;
94+} UART_Device;
95+
96+
97+//============================================================================================
98+UARTError UART_init(UART_Device* uart, uart_ctrl_t* port);
99+
100+static inline
101+UARTError UART_close(UART_Device* uart){
102+ return R_SCI_UART_Close(uart->port);
103+}
104+
105+UARTError UART_read(UART_Device* uart, void* p_dest, unsigned bytes);
106+UARTError UART_write(UART_Device* uart, const void* p_src, unsigned bytes);
107+
108+/// @brief receive data pointer
109+/// @return != NULL - pointer to receiver buffer head
110+/// == NULL - read not active
111+uint8_t* UART_rx_tail(UART_Device* uart);
112+
113+
114+static inline
115+UARTError UART_baud_set(UART_Device* uart, unsigned baud){
116+ sci_uart_instance_ctrl_t* self = (sci_uart_instance_ctrl_t*)(uart->port);
117+ return USART_set_baud(self->p_reg, baud);
118+}
119+
120+static inline
121+UARTError UART_abort(UART_Device* uart, uart_dir_t communication_to_abort){
122+ return R_SCI_UART_Abort(uart->port, communication_to_abort);
123+}
124+
125+
126+/// @brief check that R_SCI_UART_Read active
127+static inline
128+bool UART_rx_busy(UART_Device* uart){
129+ return R_SCI_UART_rx_busy(uart->port);
130+}
131+
132+/// @brief check that R_SCI_UART_Write active
133+static inline
134+bool UART_tx_busy(UART_Device* uart){
135+ return R_SCI_UART_tx_busy(uart->port);
136+}
137+
138+/// @brief check that R_SCI_UART_Write buffers empty and io sending inactive
139+bool UART_flush(UART_Device* uart);
140+
141+#if SCI_UART_CFG_DTC_SUPPORTED
142+/// @brief receive data pointer
143+/// @return != NULL - pointer to receiver buffer head
144+/// == NULL - read not active or not available
145+static inline
146+uint8_t* UART_rx_head(UART_Device* uart){
147+ return R_SCI_UART_rx_head(uart->port);
148+}
149+#endif
150+
151+
152+
153+
154+#endif /* BSP_CPU_DEV_HAL_UART_H_ */
diff -r 3a7f1912be1c -r 75d7d69b7927 cpu/renesas/ra2l.fsp/dev/r_sci_uartx.h
--- a/cpu/renesas/ra2l.fsp/dev/r_sci_uartx.h Thu Jun 02 01:29:30 2022 +0300
+++ b/cpu/renesas/ra2l.fsp/dev/r_sci_uartx.h Thu Jun 02 01:32:10 2022 +0300
@@ -52,11 +52,20 @@
5252 }
5353
5454 /// @brief check that R_SCI_UART_Write active
55-static inline
56-bool R_SCI_UART_tx_busy(uart_ctrl_t * const p_api_ctrl){
57- sci_uart_instance_ctrl_t* self = (sci_uart_instance_ctrl_t*)p_api_ctrl;
58- return self->tx_src_bytes > 0;
59-}
55+bool R_SCI_UART_tx_busy(uart_ctrl_t * p_api_ctrl);
56+
57+/// @brief receive data pointer
58+/// @return != NULL - pointer to receiver buffer tail
59+/// == NULL - read not active
60+uint8_t* R_SCI_UART_rx_tail(uart_ctrl_t * const p_api_ctrl);
61+
62+
63+#if SCI_UART_CFG_DTC_SUPPORTED
64+/// @brief receive data pointer
65+/// @return != NULL - pointer to receiver buffer head
66+/// == NULL - read not active or not available
67+uint8_t* R_SCI_UART_rx_head(uart_ctrl_t * const p_api_ctrl);
68+#endif
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