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mcuhal.arm: Commit

самопильный ХАЛ над библиотекой milandr SPL. позиционируется наличие порта порт на STM32 SPL.


Commit MetaInfo

Revisióne496f5a3c9e0f905b5db54c26d5fa1f049bed601 (tree)
Tiempo2022-06-27 02:29:55
Autoralexrayne <alexraynepe196@gmai...>
Commiteralexrayne

Log Message

+ra2l: rcc: TRNG, AES
+ mcu-conf.h - provide FSP conf detection

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Diferencia incremental

diff -r 52ab00555cb5 -r e496f5a3c9e0 cpu/renesas/ra2l.fsp/mcu-conf.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cpu/renesas/ra2l.fsp/mcu-conf.h Sun Jun 26 20:29:55 2022 +0300
@@ -0,0 +1,38 @@
1+/*
2+ * mcu-conf.h
3+ *
4+ * Created on: 10 июн. 2022 г.
5+ * Author: Lityagin Aleksandr
6+ * Author: alexrayne <alexraynepe196@gmail.com>
7+ ------------------------------------------------------------------------
8+ Generic RA2L FSP port configuration.
9+ This heder can be overriden by app
10+ */
11+
12+#ifndef BSP_CPU_MCU_CONF_H_
13+#define BSP_CPU_MCU_CONF_H_
14+
15+#include "hal_data.h"
16+
17+#if defined(R_TIMER_API_H)
18+#define MCUHAL_CONF_TIMERS
19+#endif
20+
21+#if defined(R_AGT_H)
22+// project have AGT api, can provide HAL supports on TIM_xxx API
23+#define MCUHAL_CONF_AGT
24+#endif
25+
26+#if defined(HW_SCE_PRIVATE_H)
27+// project have SCE api, can provide HAL supports on AES
28+#define MCUHAL_CONF_SCE
29+#endif
30+
31+#if defined(HW_SCE_TRNG_PRIVATE_H)
32+// project have SCE api, can provide HAL supports on AES
33+#define MCUHAL_CONF_TRNG
34+#endif
35+
36+
37+
38+#endif /* BSP_CPU_MCU_CONF_H_ */
diff -r 52ab00555cb5 -r e496f5a3c9e0 cpu/renesas/ra2l.fsp/mcu_rcc.h
--- a/cpu/renesas/ra2l.fsp/mcu_rcc.h Sun Jun 26 20:28:05 2022 +0300
+++ b/cpu/renesas/ra2l.fsp/mcu_rcc.h Sun Jun 26 20:29:55 2022 +0300
@@ -111,6 +111,12 @@
111111 void RCC_EnableClock_DMA();
112112 void RCC_DisableClock_DMA();
113113
114+void RCC_EnableClock_TRNG();
115+void RCC_DisableClock_TRNG();
116+
117+void RCC_EnableClock_AES();
118+void RCC_DisableClock_AES();
119+
114120
115121
116122 //================================================================================================
diff -r 52ab00555cb5 -r e496f5a3c9e0 cpu/renesas/ra2l.fsp/ra2l-fsp.c
--- a/cpu/renesas/ra2l.fsp/ra2l-fsp.c Sun Jun 26 20:28:05 2022 +0300
+++ b/cpu/renesas/ra2l.fsp/ra2l-fsp.c Sun Jun 26 20:29:55 2022 +0300
@@ -35,6 +35,10 @@
3535 #include <mcu-chip.h>
3636
3737
38+// this include provides access to
39+#include <mcu-conf.h>
40+
41+
3842 /////////////////////////////////////////////////////////////////////////////////////////
3943 #include "mcu_system.h"
4044 #include "arm/arm_system.cch"
@@ -196,6 +200,7 @@
196200
197201
198202 /////////////////////////////////////////////////////////////////////////////////////////
203+#if defined(MCUHAL_CONF_AGT)
199204 #include "mcu_tim.h"
200205 #include "r_agt.h"
201206
@@ -242,6 +247,7 @@
242247 CSL_FINS( (TIMx->AGTMR2), R_AGT0_AGTMR2_CKS, prescale );
243248 }
244249
250+#endif //defined(MCUHAL_CONF_AGT)
245251
246252
247253 /////////////////////////////////////////////////////////////////////////////////////////
@@ -288,6 +294,21 @@
288294 R_BSP_MODULE_STOP(FSP_IP_DTC, 0 );
289295 }
290296
297+void RCC_EnableClock_TRNG(){
298+ R_BSP_MODULE_START(FSP_IP_TRNG, 0 );
299+}
300+
301+void RCC_DisableClock_TRNG(){
302+ R_BSP_MODULE_STOP(FSP_IP_TRNG, 0 );
303+}
304+void RCC_EnableClock_AES(){
305+ R_BSP_MODULE_START(FSP_IP_AES, 0 );
306+}
307+
308+void RCC_DisableClock_AES(){
309+ R_BSP_MODULE_STOP(FSP_IP_AES, 0 );
310+}
311+
291312
292313
293314 /////////////////////////////////////////////////////////////////////////////////////////
@@ -456,3 +477,4 @@
456477 R_SYSTEM->SBYCR_b.SSBY = PDMode;
457478 R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
458479 }
480+
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