Revisión | 9 (tree) |
---|---|
Tiempo | 2012-06-13 18:35:06 |
Autor | tekken_boss |
000.001.009: 2012/06/13 18:35 : Fine tuning of SCI handshake.
@@ -15,9 +15,10 @@ | ||
15 | 15 | |
16 | 16 | #define SRCVER_MAJOR 0 |
17 | 17 | #define SRCVER_MINOR 1 |
18 | -#define SRCVER_BUILD 8 | |
18 | +#define SRCVER_BUILD 9 | |
19 | 19 | |
20 | 20 | /* -------------------------------------------------------------------- |
21 | +000.001.009: 2012/06/13 18:35 : Fine tuning of SCI handshake. | |
21 | 22 | 000.001.008: 2012/06/13 16:24 : Default setting for SCI was changed. |
22 | 23 | 000.001.007: 2012/06/13 14:45 : Fine tuning of SL811 driver class. |
23 | 24 | 000.001.006: 2012/06/11 17:01 : Fine tuning of SCI handshake. |
@@ -28,6 +28,7 @@ | ||
28 | 28 | unsigned long file_size; |
29 | 29 | unsigned long sent_bytes; |
30 | 30 | unsigned char* p_buf; |
31 | + unsigned char tx_in_progress; | |
31 | 32 | } TX_STATUS, *P_TX_STATUS; |
32 | 33 | |
33 | 34 | // ------------------------------------------- |
@@ -89,6 +90,10 @@ | ||
89 | 90 | SCI_INITIALIZE, |
90 | 91 | SCI_READY_WAIT, |
91 | 92 | SCI_IDLE = 0x80, // Idle |
93 | + SCI_DATA_SET, | |
94 | + SCI_WAIT_TX_OK, | |
95 | + | |
96 | + | |
92 | 97 | SCI_TX_IN_PROGRESS, |
93 | 98 | SCI_TX_IN_PAUSE, |
94 | 99 | SCI_TX_IN_END, |
@@ -231,8 +236,10 @@ | ||
231 | 236 | // ------------------------------------------- |
232 | 237 | #pragma interrupt (int_TXI0) |
233 | 238 | void int_TXI0(void) { |
234 | - if( serial_proc == SCI_TX_IN_PROGRESS ) { | |
239 | +// if( serial_proc == SCI_TX_IN_PROGRESS ) { | |
240 | + if( serial_proc == SCI_WAIT_TX_OK ) { | |
235 | 241 | if(SCI0.SSR.BIT.TDRE) { |
242 | +/* | |
236 | 243 | if( sci_setting.flow_control_request == FLOW_REQ_PAUSE ) { |
237 | 244 | sci_setting.flow_control_request = FLOW_REQ_NONE; |
238 | 245 | serial_proc = SCI_TX_IN_PAUSE; |
@@ -254,7 +261,9 @@ | ||
254 | 261 | } else { |
255 | 262 | SCI0.SCR.BIT.TIE = 0; // TX empty intr. disable |
256 | 263 | } |
257 | - SCI0.SSR.BIT.TDRE = 0; // TX empty intr. clear | |
264 | +*/ | |
265 | + tx_status.tx_in_progress = 0; | |
266 | + SCI0.SCR.BIT.TIE = 0; | |
258 | 267 | } |
259 | 268 | } else { |
260 | 269 | SCI0.SCR.BIT.TIE = 0; |
@@ -293,12 +302,19 @@ | ||
293 | 302 | unsigned char TransferStartRequest( unsigned char* pBuf, unsigned long size ) { |
294 | 303 | if( serial_proc != SCI_IDLE && serial_proc != SCI_TX_IN_PAUSE ) return CLASS_REQ_BUSY; |
295 | 304 | |
296 | - if( serial_proc != SCI_TX_IN_PAUSE ) { | |
305 | + if( size != 0 ) { // Start request | |
297 | 306 | tx_status.file_size = size; |
298 | 307 | tx_status.sent_bytes = 0; |
299 | 308 | tx_status.p_buf = pBuf; |
300 | - serial_proc = SCI_TX_IN_PAUSE; | |
301 | - } else { | |
309 | + tx_status.tx_in_progress = 0; | |
310 | + serial_proc = SCI_DATA_SET; | |
311 | + sci_setting.flow_control_request = FLOW_REQ_PAUSE; | |
312 | +#ifdef SCI_DEBUG_ON | |
313 | + printf("[SCI] TX Req Set\r\n"); | |
314 | +#endif | |
315 | + } | |
316 | +/* | |
317 | + else { // Continue request | |
302 | 318 | serial_proc = SCI_TX_IN_PROGRESS; |
303 | 319 | // Transfer start |
304 | 320 | switch( sci_setting.code_setting_index ) { |
@@ -317,7 +333,7 @@ | ||
317 | 333 | if(SCI0.SSR.BIT.TDRE) SCI0.SSR.BIT.TDRE = 0; // TX empty intr. clear |
318 | 334 | SCI0.SCR.BIT.TIE = 1; // TX empty intr. enable |
319 | 335 | } |
320 | - | |
336 | +*/ | |
321 | 337 | } |
322 | 338 | |
323 | 339 | // ------------------------------------------- |
@@ -354,6 +370,41 @@ | ||
354 | 370 | case SCI_IDLE: |
355 | 371 | break; |
356 | 372 | |
373 | + case SCI_DATA_SET: | |
374 | + if( sci_setting.flow_control_request != FLOW_REQ_PAUSE ) { | |
375 | + // 1 byte Transfer start | |
376 | + switch( sci_setting.code_setting_index ) { | |
377 | + case COMM_CODE_ISO: | |
378 | + SCI0.TDR = Cnv2Iso( (unsigned char) tx_status.p_buf[tx_status.sent_bytes++]); | |
379 | + break; | |
380 | + case COMM_CODE_EIA: | |
381 | + SCI0.TDR = Cnv2Eia( (unsigned char) tx_status.p_buf[tx_status.sent_bytes++]); | |
382 | + break; | |
383 | + default: | |
384 | + SCI0.TDR = (unsigned char) tx_status.p_buf[tx_status.sent_bytes++]; | |
385 | + break; | |
386 | + } | |
387 | + serial_proc = SCI_WAIT_TX_OK; | |
388 | + serial_disable_timer = 2; | |
389 | + SentBuf[tx_status.sent_bytes&0x0F] = SCI0.TDR; | |
390 | + tx_status.tx_in_progress = 1; | |
391 | + | |
392 | + if(SCI0.SSR.BIT.TDRE) SCI0.SSR.BIT.TDRE = 0; // TX empty intr. clear | |
393 | + SCI0.SCR.BIT.TIE = 1; // TX empty intr. enable | |
394 | + } | |
395 | + break; | |
396 | + | |
397 | + case SCI_WAIT_TX_OK: | |
398 | + if( tx_status.tx_in_progress ) break; | |
399 | + if( tx_status.sent_bytes >= tx_status.file_size ) { | |
400 | + SCI0.SCR.BIT.TIE = 0; //TX empty Interrupt disable | |
401 | + serial_proc = SCI_TX_IN_END; | |
402 | + serial_disable_timer = 1000; | |
403 | + } else { | |
404 | + serial_proc = SCI_DATA_SET; | |
405 | + } | |
406 | + break; | |
407 | + | |
357 | 408 | case SCI_TX_IN_PROGRESS: |
358 | 409 | if( tx_status.sent_bytes >= tx_status.file_size ) { |
359 | 410 | SCI0.SCR.BIT.TIE = 0; //TX empty Interrupt disable |
@@ -370,6 +421,9 @@ | ||
370 | 421 | break; |
371 | 422 | |
372 | 423 | case SCI_TX_IN_END: |
424 | +#ifdef SCI_DEBUG_ON | |
425 | + printf("[SCI] TX Complete\r\n"); | |
426 | +#endif | |
373 | 427 | serial_proc = SCI_IDLE; |
374 | 428 | break; |
375 | 429 |
@@ -679,6 +733,12 @@ | ||
679 | 733 | sc1602_set_buffer( 0, "SCI is ready. " ); |
680 | 734 | break; |
681 | 735 | |
736 | + case SCI_DATA_SET: | |
737 | + case SCI_WAIT_TX_OK: | |
738 | + if( sci_setting.flow_control_request == FLOW_REQ_PAUSE ) sc1602_set_buffer( 0, "Pause.... " ); | |
739 | + else sc1602_set_buffer( 0, "Sending... " ); | |
740 | + break; | |
741 | + | |
682 | 742 | case SCI_TX_IN_PROGRESS: |
683 | 743 | sc1602_set_buffer( 0, "Sending... " ); |
684 | 744 | break; |
@@ -17,6 +17,7 @@ | ||
17 | 17 | #ifdef DEBUG_ON |
18 | 18 | #define SL811HS_DEBUG_ON |
19 | 19 | #define MSCLASS_DEBUG_ON |
20 | + #define SCI_DEBUG_ON | |
20 | 21 | #endif |
21 | 22 | #define SUB_PROC_RESULT unsigned char |
22 | 23 | enum sub_proc_result_code { |