| Revisión | 481f96068e4c1c1f8ef1e38cae054b8796dff721 (tree) |
|---|---|
| Tiempo | 2022-07-26 18:29:01 |
| Autor | Peng Fan <peng.fan@nxp....> |
| Commiter | Stefano Babic |
board: freescale: imx93_evk: support ethernet
Add ethernet support
Signed-off-by: Peng Fan <peng.fan@nxp.com>
arch/arm/include/asm/arch-imx9/imx-regs.h (diff)
board/freescale/imx93_evk/imx93_evk.c (diff)
configs/imx93_11x11_evk_defconfig (diff)| @@ -7,6 +7,7 @@ | ||
| 7 | 7 | #define __ASM_ARCH_IMX9_REGS_H__ |
| 8 | 8 | |
| 9 | 9 | #define ARCH_MXC |
| 10 | +#define FEC_QUIRK_ENET_MAC | |
| 10 | 11 | |
| 11 | 12 | #define IOMUXC_BASE_ADDR 0x443C0000UL |
| 12 | 13 | #define CCM_BASE_ADDR 0x44450000UL |
| @@ -39,6 +40,12 @@ | ||
| 39 | 40 | #define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4) |
| 40 | 41 | #define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12) |
| 41 | 42 | |
| 43 | +#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1) | |
| 44 | +#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) | |
| 45 | +#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1) | |
| 46 | +#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) | |
| 47 | +#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) | |
| 48 | + | |
| 42 | 49 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
| 43 | 50 | #include <asm/types.h> |
| 44 | 51 | #include <stdbool.h> |
| @@ -38,8 +38,40 @@ int board_early_init_f(void) | ||
| 38 | 38 | return 0; |
| 39 | 39 | } |
| 40 | 40 | |
| 41 | +static int setup_fec(void) | |
| 42 | +{ | |
| 43 | + return set_clk_enet(ENET_125MHZ); | |
| 44 | +} | |
| 45 | + | |
| 46 | +int board_phy_config(struct phy_device *phydev) | |
| 47 | +{ | |
| 48 | + if (phydev->drv->config) | |
| 49 | + phydev->drv->config(phydev); | |
| 50 | + | |
| 51 | + return 0; | |
| 52 | +} | |
| 53 | + | |
| 54 | +static int setup_eqos(void) | |
| 55 | +{ | |
| 56 | + struct blk_ctrl_wakeupmix_regs *bctrl = | |
| 57 | + (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR; | |
| 58 | + | |
| 59 | + /* set INTF as RGMII, enable RGMII TXC clock */ | |
| 60 | + clrsetbits_le32(&bctrl->eqos_gpr, | |
| 61 | + BCTRL_GPR_ENET_QOS_INTF_MODE_MASK, | |
| 62 | + BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN); | |
| 63 | + | |
| 64 | + return set_clk_eqos(ENET_125MHZ); | |
| 65 | +} | |
| 66 | + | |
| 41 | 67 | int board_init(void) |
| 42 | 68 | { |
| 69 | + if (CONFIG_IS_ENABLED(FEC_MXC)) | |
| 70 | + setup_fec(); | |
| 71 | + | |
| 72 | + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) | |
| 73 | + setup_eqos(); | |
| 74 | + | |
| 43 | 75 | return 0; |
| 44 | 76 | } |
| 45 | 77 |
| @@ -75,6 +75,7 @@ CONFIG_ENV_IS_IN_MMC=y | ||
| 75 | 75 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 76 | 76 | CONFIG_SYS_MMC_ENV_DEV=1 |
| 77 | 77 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 78 | +CONFIG_NET_RANDOM_ETHADDR=y | |
| 78 | 79 | CONFIG_SPL_DM=y |
| 79 | 80 | CONFIG_REGMAP=y |
| 80 | 81 | CONFIG_SYSCON=y |
| @@ -89,6 +90,14 @@ CONFIG_MMC_UHS_SUPPORT=y | ||
| 89 | 90 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 90 | 91 | CONFIG_MMC_HS400_SUPPORT=y |
| 91 | 92 | CONFIG_FSL_USDHC=y |
| 93 | +CONFIG_PHY_REALTEK=y | |
| 94 | +CONFIG_DM_ETH=y | |
| 95 | +CONFIG_DM_ETH_PHY=y | |
| 96 | +CONFIG_PHY_GIGE=y | |
| 97 | +CONFIG_DWC_ETH_QOS=y | |
| 98 | +CONFIG_DWC_ETH_QOS_IMX=y | |
| 99 | +CONFIG_FEC_MXC=y | |
| 100 | +CONFIG_MII=y | |
| 92 | 101 | CONFIG_PINCTRL=y |
| 93 | 102 | CONFIG_SPL_PINCTRL=y |
| 94 | 103 | CONFIG_PINCTRL_IMX93=y |
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