Commit: fc97ff2695d6d7fbea7d5fda7b080f405d6ee744 - uboot (git)

Commit MetaInfo

• Revisión: fc97ff2695d6d7fbea7d5fda7b080f405d6ee744 (tree)
• Tiempo: 2022-07-19 23:52:15
• Autor: Tom Rini <trini@kons...>
• Commiter: Tom Rini

Log Message

Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi

To quote Andre:

One prominent feature is the restructering of the clock driver, which
allows to end up with one actual driver for all variants, although we
still only compile in support for one SoC.
Also contained are some initial SPI fixes, which should fix some
problems, and enable SPI flash support for the F1C100s SoC. Those
patches revealed more problems, I will queue fixes later on, but for
now it should at least still work.
Apart from some smaller fixes (for instance for NAND operation), there
is also preparation for the upcoming Allwinner D1 support, in form of
the USB PHY driver. There are more driver support patches to come.

The gitlab CI completed successfully, including the build test for all
160 sunxi boards. I also boot tested on a few boards, but didn't have
time for more elaborate tests this time.

Cambiar Resumen

• modified: arch/arm/mach-sunxi/Kconfig
• modified: configs/licheepi_nano_defconfig
• modified: configs/orangepi_zero_defconfig
• modified: drivers/clk/sunxi/clk_a10.c
• modified: drivers/clk/sunxi/clk_a10s.c
• modified: drivers/clk/sunxi/clk_a23.c
• modified: drivers/clk/sunxi/clk_a31.c
• modified: drivers/clk/sunxi/clk_a31_r.c
• modified: drivers/clk/sunxi/clk_a64.c
• modified: drivers/clk/sunxi/clk_a80.c
• modified: drivers/clk/sunxi/clk_a83t.c
• modified: drivers/clk/sunxi/clk_f1c100s.c
• modified: drivers/clk/sunxi/clk_h3.c
• modified: drivers/clk/sunxi/clk_h6.c
• modified: drivers/clk/sunxi/clk_h616.c
• modified: drivers/clk/sunxi/clk_h6_r.c
• modified: drivers/clk/sunxi/clk_r40.c
• modified: drivers/clk/sunxi/clk_sunxi.c
• modified: drivers/clk/sunxi/clk_v3s.c
• modified: drivers/mtd/nand/raw/sunxi_nand_spl.c
• modified: drivers/net/sun8i_emac.c
• modified: drivers/phy/allwinner/Kconfig
• modified: drivers/phy/allwinner/phy-sun4i-usb.c
• modified: drivers/reset/reset-sunxi.c
• modified: drivers/spi/spi-sunxi.c
• modified: include/clk/sunxi.h
• modified: include/configs/sun4i.h
• modified: include/configs/sun50i.h
• modified: include/configs/sun5i.h
• modified: include/configs/sun6i.h
• modified: include/configs/sun7i.h
• modified: include/configs/sun8i.h
• modified: include/configs/sun9i.h
• modified: include/configs/suniv.h

Diferencia incremental

--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -679,15 +679,6 @@ config MMC_SUNXI_SLOT_EXTRA
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
 
-config INITIAL_USB_SCAN_DELAY
-	int "delay initial usb scan by x ms to allow builtin devices to init"
-	default 0
-	---help---
-	Some boards have on board usb devices which need longer than the
-	USB spec's 1 second to connect from board powerup. Set this config
-	option to a non 0 value to add an extra delay before the first usb
-	bus scan.
-
 config USB0_VBUS_PIN
 	string "Vbus enable pin for usb0 (otg)"
 	default ""
@@ -850,8 +841,9 @@ config VIDEO_LCD_DCLK_PHASE
 	int "LCD panel display clock phase"
 	depends on VIDEO_SUNXI || DM_VIDEO
 	default 1
+	range 0 3
 	---help---
-	Select LCD panel display clock phase shift, range 0-3.
+	Select LCD panel display clock phase shift
 
 config VIDEO_LCD_POWER
 	string "LCD panel power enable pin"

--- a/configs/licheepi_nano_defconfig
+++ b/configs/licheepi_nano_defconfig
@@ -13,3 +13,6 @@ CONFIG_SPL_SPI_SUNXI=y
 CONFIG_SPL_STACK=0x8000
 CONFIG_SYS_PBSIZE=1024
 # CONFIG_SYSRESET is not set
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI=y

--- a/configs/orangepi_zero_defconfig
+++ b/configs/orangepi_zero_defconfig
@@ -10,6 +10,7 @@ CONFIG_SPL_SPI_SUNXI=y
 CONFIG_CONSOLE_MUX=y
 CONFIG_SPL_STACK=0x8000
 CONFIG_SYS_PBSIZE=1024
+CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SUN8I_EMAC=y
 CONFIG_SPI=y

--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -64,30 +64,9 @@ static struct ccu_reset a10_resets[] = {
 	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
 };
 
-static const struct ccu_desc a10_ccu_desc = {
+const struct ccu_desc a10_ccu_desc = {
 	.gates = a10_gates,
 	.resets = a10_resets,
-};
-
-static int a10_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
-}
-
-static const struct udevice_id a10_ccu_ids[] = {
-	{ .compatible = "allwinner,sun4i-a10-ccu",
-	  .data = (ulong)&a10_ccu_desc },
-	{ .compatible = "allwinner,sun7i-a20-ccu",
-	  .data = (ulong)&a10_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun4i_a10) = {
-	.name		= "sun4i_a10_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a10_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a10_clk_bind,
+	.num_gates = ARRAY_SIZE(a10_gates),
+	.num_resets = ARRAY_SIZE(a10_resets),
 };

--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -49,30 +49,9 @@ static struct ccu_reset a10s_resets[] = {
 	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
 };
 
-static const struct ccu_desc a10s_ccu_desc = {
+const struct ccu_desc a10s_ccu_desc = {
 	.gates = a10s_gates,
 	.resets = a10s_resets,
-};
-
-static int a10s_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a10s_resets));
-}
-
-static const struct udevice_id a10s_ccu_ids[] = {
-	{ .compatible = "allwinner,sun5i-a10s-ccu",
-	  .data = (ulong)&a10s_ccu_desc },
-	{ .compatible = "allwinner,sun5i-a13-ccu",
-	  .data = (ulong)&a10s_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun5i_a10s) = {
-	.name		= "sun5i_a10s_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a10s_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a10s_clk_bind,
+	.num_gates = ARRAY_SIZE(a10s_gates),
+	.num_resets = ARRAY_SIZE(a10s_resets),
 };

--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -68,30 +68,9 @@ static struct ccu_reset a23_resets[] = {
 	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
-static const struct ccu_desc a23_ccu_desc = {
+const struct ccu_desc a23_ccu_desc = {
 	.gates = a23_gates,
 	.resets = a23_resets,
-};
-
-static int a23_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets));
-}
-
-static const struct udevice_id a23_clk_ids[] = {
-	{ .compatible = "allwinner,sun8i-a23-ccu",
-	  .data = (ulong)&a23_ccu_desc },
-	{ .compatible = "allwinner,sun8i-a33-ccu",
-	  .data = (ulong)&a23_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun8i_a23) = {
-	.name		= "sun8i_a23_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a23_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a23_clk_bind,
+	.num_gates = ARRAY_SIZE(a23_gates),
+	.num_resets = ARRAY_SIZE(a23_resets),
 };

--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -89,28 +89,9 @@ static struct ccu_reset a31_resets[] = {
 	[RST_APB2_UART5]	= RESET(0x2d8, BIT(21)),
 };
 
-static const struct ccu_desc a31_ccu_desc = {
+const struct ccu_desc a31_ccu_desc = {
 	.gates = a31_gates,
 	.resets = a31_resets,
-};
-
-static int a31_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
-}
-
-static const struct udevice_id a31_clk_ids[] = {
-	{ .compatible = "allwinner,sun6i-a31-ccu",
-	  .data = (ulong)&a31_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun6i_a31) = {
-	.name		= "sun6i_a31_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a31_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a31_clk_bind,
+	.num_gates = ARRAY_SIZE(a31_gates),
+	.num_resets = ARRAY_SIZE(a31_resets),
 };

--- a/drivers/clk/sunxi/clk_a31_r.c
+++ b/drivers/clk/sunxi/clk_a31_r.c
@@ -28,32 +28,9 @@ static struct ccu_reset a31_r_resets[] = {
 	[RST_APB0_I2C]		= RESET(0x0b0, BIT(6)),
 };
 
-static const struct ccu_desc a31_r_ccu_desc = {
+const struct ccu_desc a31_r_ccu_desc = {
 	.gates = a31_r_gates,
 	.resets = a31_r_resets,
-};
-
-static int a31_r_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
-}
-
-static const struct udevice_id a31_r_clk_ids[] = {
-	{ .compatible = "allwinner,sun8i-a83t-r-ccu",
-	  .data = (ulong)&a31_r_ccu_desc },
-	{ .compatible = "allwinner,sun8i-h3-r-ccu",
-	  .data = (ulong)&a31_r_ccu_desc },
-	{ .compatible = "allwinner,sun50i-a64-r-ccu",
-	  .data = (ulong)&a31_r_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun6i_a31_r) = {
-	.name		= "sun6i_a31_r_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a31_r_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a31_r_clk_bind,
+	.num_gates = ARRAY_SIZE(a31_r_gates),
+	.num_resets = ARRAY_SIZE(a31_r_resets),
 };

--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -77,28 +77,9 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
-static const struct ccu_desc a64_ccu_desc = {
+const struct ccu_desc a64_ccu_desc = {
 	.gates = a64_gates,
 	.resets = a64_resets,
-};
-
-static int a64_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
-}
-
-static const struct udevice_id a64_ccu_ids[] = {
-	{ .compatible = "allwinner,sun50i-a64-ccu",
-	  .data = (ulong)&a64_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun50i_a64) = {
-	.name		= "sun50i_a64_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a64_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a64_clk_bind,
+	.num_gates = ARRAY_SIZE(a64_gates),
+	.num_resets = ARRAY_SIZE(a64_resets),
 };

--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -74,40 +74,16 @@ static const struct ccu_reset a80_mmc_resets[] = {
 	[3]			= GATE(0xc, BIT(18)),
 };
 
-static const struct ccu_desc a80_ccu_desc = {
+const struct ccu_desc a80_ccu_desc = {
 	.gates = a80_gates,
 	.resets = a80_resets,
+	.num_gates = ARRAY_SIZE(a80_gates),
+	.num_resets = ARRAY_SIZE(a80_resets),
 };
 
-static const struct ccu_desc a80_mmc_clk_desc = {
+const struct ccu_desc a80_mmc_clk_desc = {
 	.gates = a80_mmc_gates,
 	.resets = a80_mmc_resets,
-};
-
-static int a80_clk_bind(struct udevice *dev)
-{
-	ulong count = ARRAY_SIZE(a80_resets);
-
-	if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
-		count = ARRAY_SIZE(a80_mmc_resets);
-
-	return sunxi_reset_bind(dev, count);
-}
-
-static const struct udevice_id a80_ccu_ids[] = {
-	{ .compatible = "allwinner,sun9i-a80-ccu",
-	  .data = (ulong)&a80_ccu_desc },
-	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
-	  .data = (ulong)&a80_mmc_clk_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun9i_a80) = {
-	.name		= "sun9i_a80_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a80_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a80_clk_bind,
+	.num_gates = ARRAY_SIZE(a80_mmc_gates),
+	.num_resets = ARRAY_SIZE(a80_mmc_resets),
 };

--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -72,28 +72,9 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
 };
 
-static const struct ccu_desc a83t_ccu_desc = {
+const struct ccu_desc a83t_ccu_desc = {
 	.gates = a83t_gates,
 	.resets = a83t_resets,
-};
-
-static int a83t_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
-}
-
-static const struct udevice_id a83t_clk_ids[] = {
-	{ .compatible = "allwinner,sun8i-a83t-ccu",
-	  .data = (ulong)&a83t_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun8i_a83t) = {
-	.name		= "sun8i_a83t_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= a83t_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= a83t_clk_bind,
+	.num_gates = ARRAY_SIZE(a83t_gates),
+	.num_resets = ARRAY_SIZE(a83t_resets),
 };

--- a/drivers/clk/sunxi/clk_f1c100s.c
+++ b/drivers/clk/sunxi/clk_f1c100s.c
@@ -47,28 +47,9 @@ static struct ccu_reset f1c100s_resets[] = {
 	[RST_BUS_UART2]		= RESET(0x2d0, BIT(22)),
 };
 
-static const struct ccu_desc f1c100s_ccu_desc = {
+const struct ccu_desc f1c100s_ccu_desc = {
 	.gates = f1c100s_gates,
 	.resets = f1c100s_resets,
-};
-
-static int f1c100s_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(f1c100s_resets));
-}
-
-static const struct udevice_id f1c100s_clk_ids[] = {
-	{ .compatible = "allwinner,suniv-f1c100s-ccu",
-	  .data = (ulong)&f1c100s_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_suniv_f1c100s) = {
-	.name		= "suniv_f1c100s_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= f1c100s_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= f1c100s_clk_bind,
+	.num_gates = ARRAY_SIZE(f1c100s_gates),
+	.num_resets = ARRAY_SIZE(f1c100s_resets),
 };

--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -90,30 +90,9 @@ static struct ccu_reset h3_resets[] = {
 	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
 };
 
-static const struct ccu_desc h3_ccu_desc = {
+const struct ccu_desc h3_ccu_desc = {
 	.gates = h3_gates,
 	.resets = h3_resets,
-};
-
-static int h3_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
-}
-
-static const struct udevice_id h3_ccu_ids[] = {
-	{ .compatible = "allwinner,sun8i-h3-ccu",
-	  .data = (ulong)&h3_ccu_desc },
-	{ .compatible = "allwinner,sun50i-h5-ccu",
-	  .data = (ulong)&h3_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun8i_h3) = {
-	.name		= "sun8i_h3_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= h3_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= h3_clk_bind,
+	.num_gates = ARRAY_SIZE(h3_gates),
+	.num_resets = ARRAY_SIZE(h3_resets),
 };

--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -91,28 +91,9 @@ static struct ccu_reset h6_resets[] = {
 	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
 };
 
-static const struct ccu_desc h6_ccu_desc = {
+const struct ccu_desc h6_ccu_desc = {
 	.gates = h6_gates,
 	.resets = h6_resets,
-};
-
-static int h6_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(h6_resets));
-}
-
-static const struct udevice_id h6_ccu_ids[] = {
-	{ .compatible = "allwinner,sun50i-h6-ccu",
-	  .data = (ulong)&h6_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun50i_h6) = {
-	.name		= "sun50i_h6_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= h6_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= h6_clk_bind,
+	.num_gates = ARRAY_SIZE(h6_gates),
+	.num_resets = ARRAY_SIZE(h6_resets),
 };

--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -109,28 +109,9 @@ static struct ccu_reset h616_resets[] = {
 	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
 };
 
-static const struct ccu_desc h616_ccu_desc = {
+const struct ccu_desc h616_ccu_desc = {
 	.gates = h616_gates,
 	.resets = h616_resets,
-};
-
-static int h616_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(h616_resets));
-}
-
-static const struct udevice_id h616_ccu_ids[] = {
-	{ .compatible = "allwinner,sun50i-h616-ccu",
-	  .data = (ulong)&h616_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun50i_h616) = {
-	.name		= "sun50i_h616_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= h616_ccu_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= h616_clk_bind,
+	.num_gates = ARRAY_SIZE(h616_gates),
+	.num_resets = ARRAY_SIZE(h616_resets),
 };

--- a/drivers/clk/sunxi/clk_h6_r.c
+++ b/drivers/clk/sunxi/clk_h6_r.c
@@ -34,30 +34,9 @@ static struct ccu_reset h6_r_resets[] = {
 	[RST_R_APB1_W1]		= RESET(0x1ec, BIT(16)),
 };
 
-static const struct ccu_desc h6_r_ccu_desc = {
+const struct ccu_desc h6_r_ccu_desc = {
 	.gates = h6_r_gates,
 	.resets = h6_r_resets,
-};
-
-static int h6_r_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
-}
-
-static const struct udevice_id h6_r_clk_ids[] = {
-	{ .compatible = "allwinner,sun50i-h6-r-ccu",
-	  .data = (ulong)&h6_r_ccu_desc },
-	{ .compatible = "allwinner,sun50i-h616-r-ccu",
-	  .data = (ulong)&h6_r_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun50i_h6_r) = {
-	.name		= "sun50i_h6_r_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= h6_r_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= h6_r_clk_bind,
+	.num_gates = ARRAY_SIZE(h6_r_gates),
+	.num_resets = ARRAY_SIZE(h6_r_resets),
 };

--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -99,28 +99,9 @@ static struct ccu_reset r40_resets[] = {
 	[RST_BUS_UART7]		= RESET(0x2d8, BIT(23)),
 };
 
-static const struct ccu_desc r40_ccu_desc = {
+const struct ccu_desc r40_ccu_desc = {
 	.gates = r40_gates,
 	.resets = r40_resets,
-};
-
-static int r40_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
-}
-
-static const struct udevice_id r40_clk_ids[] = {
-	{ .compatible = "allwinner,sun8i-r40-ccu",
-	  .data = (ulong)&r40_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun8i_r40) = {
-	.name		= "sun8i_r40_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= r40_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= r40_clk_bind,
+	.num_gates = ARRAY_SIZE(r40_gates),
+	.num_resets = ARRAY_SIZE(r40_resets),
 };

--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -12,25 +12,31 @@
 #include <reset.h>
 #include <asm/io.h>
 #include <clk/sunxi.h>
+#include <dm/device-internal.h>
 #include <linux/bitops.h>
 #include <linux/log2.h>
 
-static const struct ccu_clk_gate *priv_to_gate(struct ccu_priv *priv,
+extern U_BOOT_DRIVER(sunxi_reset);
+
+static const struct ccu_clk_gate *plat_to_gate(struct ccu_plat *plat,
 					       unsigned long id)
 {
-	return &priv->desc->gates[id];
+	if (id >= plat->desc->num_gates)
+		return NULL;
+
+	return &plat->desc->gates[id];
 }
 
 static int sunxi_set_gate(struct clk *clk, bool on)
 {
-	struct ccu_priv *priv = dev_get_priv(clk->dev);
-	const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
+	struct ccu_plat *plat = dev_get_plat(clk->dev);
+	const struct ccu_clk_gate *gate = plat_to_gate(plat, clk->id);
 	u32 reg;
 
-	if ((gate->flags & CCU_CLK_F_DUMMY_GATE))
+	if (gate && (gate->flags & CCU_CLK_F_DUMMY_GATE))
 		return 0;
 
-	if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
+	if (!gate || !(gate->flags & CCU_CLK_F_IS_VALID)) {
 		printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
 		return 0;
 	}
@@ -38,13 +44,13 @@ static int sunxi_set_gate(struct clk *clk, bool on)
 	debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
 	      clk->id, gate->off, ilog2(gate->bit));
 
-	reg = readl(priv->base + gate->off);
+	reg = readl(plat->base + gate->off);
 	if (on)
 		reg |= gate->bit;
 	else
 		reg &= ~gate->bit;
 
-	writel(reg, priv->base + gate->off);
+	writel(reg, plat->base + gate->off);
 
 	return 0;
 }
@@ -64,21 +70,19 @@ struct clk_ops sunxi_clk_ops = {
 	.disable = sunxi_clk_disable,
 };
 
-int sunxi_clk_probe(struct udevice *dev)
+static int sunxi_clk_bind(struct udevice *dev)
+{
+	/* Reuse the platform data for the reset driver. */
+	return device_bind(dev, DM_DRIVER_REF(sunxi_reset), "reset",
+			   dev_get_plat(dev), dev_ofnode(dev), NULL);
+}
+
+static int sunxi_clk_probe(struct udevice *dev)
 {
-	struct ccu_priv *priv = dev_get_priv(dev);
 	struct clk_bulk clk_bulk;
 	struct reset_ctl_bulk rst_bulk;
 	int ret;
 
-	priv->base = dev_read_addr_ptr(dev);
-	if (!priv->base)
-		return -ENOMEM;
-
-	priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
-	if (!priv->desc)
-		return -EINVAL;
-
 	ret = clk_get_bulk(dev, &clk_bulk);
 	if (!ret)
 		clk_enable_bulk(&clk_bulk);
@@ -89,3 +93,138 @@ int sunxi_clk_probe(struct udevice *dev)
 
 	return 0;
 }
+
+static int sunxi_clk_of_to_plat(struct udevice *dev)
+{
+	struct ccu_plat *plat = dev_get_plat(dev);
+
+	plat->base = dev_read_addr_ptr(dev);
+	if (!plat->base)
+		return -ENOMEM;
+
+	plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
+	if (!plat->desc)
+		return -EINVAL;
+
+	return 0;
+}
+
+extern const struct ccu_desc a10_ccu_desc;
+extern const struct ccu_desc a10s_ccu_desc;
+extern const struct ccu_desc a23_ccu_desc;
+extern const struct ccu_desc a31_ccu_desc;
+extern const struct ccu_desc a31_r_ccu_desc;
+extern const struct ccu_desc a64_ccu_desc;
+extern const struct ccu_desc a80_ccu_desc;
+extern const struct ccu_desc a80_mmc_clk_desc;
+extern const struct ccu_desc a83t_ccu_desc;
+extern const struct ccu_desc f1c100s_ccu_desc;
+extern const struct ccu_desc h3_ccu_desc;
+extern const struct ccu_desc h6_ccu_desc;
+extern const struct ccu_desc h616_ccu_desc;
+extern const struct ccu_desc h6_r_ccu_desc;
+extern const struct ccu_desc r40_ccu_desc;
+extern const struct ccu_desc v3s_ccu_desc;
+
+static const struct udevice_id sunxi_clk_ids[] = {
+#ifdef CONFIG_CLK_SUN4I_A10
+	{ .compatible = "allwinner,sun4i-a10-ccu",
+	  .data = (ulong)&a10_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN5I_A10S
+	{ .compatible = "allwinner,sun5i-a10s-ccu",
+	  .data = (ulong)&a10s_ccu_desc },
+	{ .compatible = "allwinner,sun5i-a13-ccu",
+	  .data = (ulong)&a10s_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN6I_A31
+	{ .compatible = "allwinner,sun6i-a31-ccu",
+	  .data = (ulong)&a31_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN4I_A10
+	{ .compatible = "allwinner,sun7i-a20-ccu",
+	  .data = (ulong)&a10_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN8I_A23
+	{ .compatible = "allwinner,sun8i-a23-ccu",
+	  .data = (ulong)&a23_ccu_desc },
+	{ .compatible = "allwinner,sun8i-a33-ccu",
+	  .data = (ulong)&a23_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN8I_A83T
+	{ .compatible = "allwinner,sun8i-a83t-ccu",
+	  .data = (ulong)&a83t_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN6I_A31_R
+	{ .compatible = "allwinner,sun8i-a83t-r-ccu",
+	  .data = (ulong)&a31_r_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN8I_H3
+	{ .compatible = "allwinner,sun8i-h3-ccu",
+	  .data = (ulong)&h3_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN6I_A31_R
+	{ .compatible = "allwinner,sun8i-h3-r-ccu",
+	  .data = (ulong)&a31_r_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN8I_R40
+	{ .compatible = "allwinner,sun8i-r40-ccu",
+	  .data = (ulong)&r40_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN8I_V3S
+	{ .compatible = "allwinner,sun8i-v3-ccu",
+	  .data = (ulong)&v3s_ccu_desc },
+	{ .compatible = "allwinner,sun8i-v3s-ccu",
+	  .data = (ulong)&v3s_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN9I_A80
+	{ .compatible = "allwinner,sun9i-a80-ccu",
+	  .data = (ulong)&a80_ccu_desc },
+	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
+	  .data = (ulong)&a80_mmc_clk_desc },
+#endif
+#ifdef CONFIG_CLK_SUN50I_A64
+	{ .compatible = "allwinner,sun50i-a64-ccu",
+	  .data = (ulong)&a64_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN6I_A31_R
+	{ .compatible = "allwinner,sun50i-a64-r-ccu",
+	  .data = (ulong)&a31_r_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN8I_H3
+	{ .compatible = "allwinner,sun50i-h5-ccu",
+	  .data = (ulong)&h3_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN50I_H6
+	{ .compatible = "allwinner,sun50i-h6-ccu",
+	  .data = (ulong)&h6_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN50I_H6_R
+	{ .compatible = "allwinner,sun50i-h6-r-ccu",
+	  .data = (ulong)&h6_r_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN50I_H616
+	{ .compatible = "allwinner,sun50i-h616-ccu",
+	  .data = (ulong)&h616_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN50I_H6_R
+	{ .compatible = "allwinner,sun50i-h616-r-ccu",
+	  .data = (ulong)&h6_r_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUNIV_F1C100S
+	{ .compatible = "allwinner,suniv-f1c100s-ccu",
+	  .data = (ulong)&f1c100s_ccu_desc },
+#endif
+	{ }
+};
+
+U_BOOT_DRIVER(sunxi_clk) = {
+	.name		= "sunxi_clk",
+	.id		= UCLASS_CLK,
+	.of_match	= sunxi_clk_ids,
+	.bind		= sunxi_clk_bind,
+	.probe		= sunxi_clk_probe,
+	.of_to_plat	= sunxi_clk_of_to_plat,
+	.plat_auto	= sizeof(struct ccu_plat),
+	.ops		= &sunxi_clk_ops,
+};

--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -49,30 +49,9 @@ static struct ccu_reset v3s_resets[] = {
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
 };
 
-static const struct ccu_desc v3s_ccu_desc = {
+const struct ccu_desc v3s_ccu_desc = {
 	.gates = v3s_gates,
 	.resets = v3s_resets,
-};
-
-static int v3s_clk_bind(struct udevice *dev)
-{
-	return sunxi_reset_bind(dev, ARRAY_SIZE(v3s_resets));
-}
-
-static const struct udevice_id v3s_clk_ids[] = {
-	{ .compatible = "allwinner,sun8i-v3s-ccu",
-	  .data = (ulong)&v3s_ccu_desc },
-	{ .compatible = "allwinner,sun8i-v3-ccu",
-	  .data = (ulong)&v3s_ccu_desc },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_sun8i_v3s) = {
-	.name		= "sun8i_v3s_ccu",
-	.id		= UCLASS_CLK,
-	.of_match	= v3s_clk_ids,
-	.priv_auto	= sizeof(struct ccu_priv),
-	.ops		= &sunxi_clk_ops,
-	.probe		= sunxi_clk_probe,
-	.bind		= v3s_clk_bind,
+	.num_gates = ARRAY_SIZE(v3s_gates),
+	.num_resets = ARRAY_SIZE(v3s_resets),
 };

--- a/drivers/mtd/nand/raw/sunxi_nand_spl.c
+++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c
@@ -208,7 +208,7 @@ static void nand_apply_config(const struct nfc_config *conf)
 
 	val = readl(SUNXI_NFC_BASE + NFC_CTL);
 	val &= ~NFC_CTL_PAGE_SIZE_MASK;
-	writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
+	writel(val | NFC_CTL_PAGE_SIZE(conf->page_size),
 	       SUNXI_NFC_BASE + NFC_CTL);
 	writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
 	writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);

--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -16,7 +16,6 @@
 #include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
@@ -857,7 +856,7 @@ static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
 	priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 
 	pdata->phy_interface = dev_read_phy_mode(dev);
-	printf("phy interface%d\n", pdata->phy_interface);
+	debug("phy interface %d\n", pdata->phy_interface);
 	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
 		return -EINVAL;
 

--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -13,6 +13,16 @@ config PHY_SUN4I_USB
 	  This driver controls the entire USB PHY block, both the USB OTG
 	  parts, as well as the 2 regular USB 2 host PHYs.
 
+config INITIAL_USB_SCAN_DELAY
+	int "Delay initial USB scan by x ms to allow builtin devices to init"
+	depends on PHY_SUN4I_USB
+	default 0
+	help
+	  Some boards have on board usb devices which need longer than
+	  the USB spec's 1 second to connect from board powerup. Set
+	  this option to a nonzero value to add an extra delay before
+	  the first USB bus scan.
+
 config PHY_SUN50I_USB3
 	bool "Allwinner sun50i USB3 PHY driver"
 	depends on ARCH_SUNXI

--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -20,8 +20,6 @@
 #include <reset.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
 #include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
@@ -34,7 +32,8 @@
 #define REG_PHYTUNE			0x0c
 #define REG_PHYCTL_A33			0x10
 #define REG_PHY_OTGCTL			0x20
-#define REG_PMU_UNK1			0x10
+
+#define REG_HCI_PHY_CTL			0x10
 
 /* Common Control Bits for Both PHYs */
 #define PHY_PLL_BW			0x03
@@ -65,6 +64,7 @@
 /* A83T specific control bits for PHY0 */
 #define PHY_CTL_VBUSVLDEXT		BIT(5)
 #define PHY_CTL_SIDDQ			BIT(3)
+#define PHY_CTL_H3_SIDDQ		BIT(1)
 
 /* A83T specific control bits for PHY2 HSIC */
 #define SUNXI_EHCI_HS_FORCE		BIT(20)
@@ -89,9 +89,9 @@ struct sun4i_usb_phy_cfg {
 	int num_phys;
 	enum sun4i_usb_phy_type type;
 	u32 disc_thresh;
+	u32 hci_phy_ctl_clear;
 	u8 phyctl_offset;
 	bool dedicated_clocks;
-	bool enable_pmu_unk1;
 	bool phy0_dual_route;
 	int missing_phys;
 };
@@ -277,6 +277,12 @@ static int sun4i_usb_phy_init(struct phy *phy)
 		return ret;
 	}
 
+	if (usb_phy->pmu && data->cfg->hci_phy_ctl_clear) {
+		val = readl(usb_phy->pmu + REG_HCI_PHY_CTL);
+		val &= ~data->cfg->hci_phy_ctl_clear;
+		writel(val, usb_phy->pmu + REG_HCI_PHY_CTL);
+	}
+
 	if (data->cfg->type == sun8i_a83t_phy ||
 	    data->cfg->type == sun50i_h6_phy) {
 		if (phy->id == 0) {
@@ -286,11 +292,6 @@ static int sun4i_usb_phy_init(struct phy *phy)
 			writel(val, data->base + data->cfg->phyctl_offset);
 		}
 	} else {
-		if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
-			val = readl(usb_phy->pmu + REG_PMU_UNK1);
-			writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
-		}
-
 		if (usb_phy->id == 0)
 			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
 					    PHY_RES45_CAL_DATA,
@@ -530,7 +531,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -539,7 +539,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -548,7 +547,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -557,7 +555,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = false,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -566,7 +563,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -575,7 +571,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = false,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
@@ -591,7 +586,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 	.phy0_dual_route = true,
 };
 
@@ -601,7 +596,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 	.phy0_dual_route = true,
 };
 
@@ -611,7 +606,16 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
+	.phy0_dual_route = true,
+};
+
+static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
+	.num_phys = 2,
+	.type = sun50i_h6_phy,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
 	.phy0_dual_route = true,
 };
 
@@ -621,7 +625,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
+	.hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
 	.phy0_dual_route = true,
 };
 
@@ -631,7 +635,6 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
-	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 	.missing_phys = BIT(1) | BIT(2),
 };
@@ -647,6 +650,7 @@ static const struct udevice_id sun4i_usb_phy_ids[] = {
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
 	{ .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
+	{ .compatible = "allwinner,sun20i-d1-usb-phy", .data = (ulong)&sun20i_d1_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
 	{ }

--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -12,30 +12,22 @@
 #include <reset-uclass.h>
 #include <asm/io.h>
 #include <clk/sunxi.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
 #include <linux/bitops.h>
 #include <linux/log2.h>
 
-struct sunxi_reset_priv {
-	void *base;
-	ulong count;
-	const struct ccu_desc *desc;
-};
-
-static const struct ccu_reset *priv_to_reset(struct sunxi_reset_priv *priv,
+static const struct ccu_reset *plat_to_reset(struct ccu_plat *plat,
 					     unsigned long id)
 {
-	return	&priv->desc->resets[id];
+	return	&plat->desc->resets[id];
 }
 
 static int sunxi_reset_request(struct reset_ctl *reset_ctl)
 {
-	struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+	struct ccu_plat *plat = dev_get_plat(reset_ctl->dev);
 
 	debug("%s: (RST#%ld)\n", __func__, reset_ctl->id);
 
-	if (reset_ctl->id >= priv->count)
+	if (reset_ctl->id >= plat->desc->num_resets)
 		return -EINVAL;
 
 	return 0;
@@ -43,8 +35,8 @@ static int sunxi_reset_request(struct reset_ctl *reset_ctl)
 
 static int sunxi_set_reset(struct reset_ctl *reset_ctl, bool on)
 {
-	struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev);
-	const struct ccu_reset *reset = priv_to_reset(priv, reset_ctl->id);
+	struct ccu_plat *plat = dev_get_plat(reset_ctl->dev);
+	const struct ccu_reset *reset = plat_to_reset(plat, reset_ctl->id);
 	u32 reg;
 
 	if (!(reset->flags & CCU_RST_F_IS_VALID)) {
@@ -55,13 +47,13 @@ static int sunxi_set_reset(struct reset_ctl *reset_ctl, bool on)
 	debug("%s: (RST#%ld) off#0x%x, BIT(%d)\n", __func__,
 	      reset_ctl->id, reset->off, ilog2(reset->bit));
 
-	reg = readl(priv->base + reset->off);
+	reg = readl(plat->base + reset->off);
 	if (on)
 		reg |= reset->bit;
 	else
 		reg &= ~reset->bit;
 
-	writel(reg, priv->base + reset->off);
+	writel(reg, plat->base + reset->off);
 
 	return 0;
 }
@@ -82,39 +74,8 @@ struct reset_ops sunxi_reset_ops = {
 	.rst_deassert = sunxi_reset_deassert,
 };
 
-static int sunxi_reset_probe(struct udevice *dev)
-{
-	struct sunxi_reset_priv *priv = dev_get_priv(dev);
-
-	priv->base = dev_read_addr_ptr(dev);
-
-	return 0;
-}
-
-int sunxi_reset_bind(struct udevice *dev, ulong count)
-{
-	struct udevice *rst_dev;
-	struct sunxi_reset_priv *priv;
-	int ret;
-
-	ret = device_bind_driver_to_node(dev, "sunxi_reset", "reset",
-					 dev_ofnode(dev), &rst_dev);
-	if (ret) {
-		debug("failed to bind sunxi_reset driver (ret=%d)\n", ret);
-		return ret;
-	}
-	priv = malloc(sizeof(struct sunxi_reset_priv));
-	priv->count = count;
-	priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
-	dev_set_priv(rst_dev, priv);
-
-	return 0;
-}
-
 U_BOOT_DRIVER(sunxi_reset) = {
 	.name		= "sunxi_reset",
 	.id		= UCLASS_RESET,
 	.ops		= &sunxi_reset_ops,
-	.probe		= sunxi_reset_probe,
-	.priv_auto	= sizeof(struct sunxi_reset_priv),
 };

--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -72,10 +72,18 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SUN4I_XMIT_CNT(cnt)		((cnt) & SUN4I_MAX_XFER_SIZE)
 #define SUN4I_FIFO_STA_RF_CNT_BITS	0
 
-#define SUN4I_SPI_MAX_RATE		24000000
+#ifdef CONFIG_MACH_SUNIV
+/* the AHB clock, which we programmed to be 1/3 of PLL_PERIPH@600MHz */
+#define SUNXI_INPUT_CLOCK		200000000	/* 200 MHz */
+#define SUN4I_SPI_MAX_RATE		(SUNXI_INPUT_CLOCK / 2)
+#else
+/* the SPI mod clock, defaulting to be 1/1 of the HOSC@24MHz */
+#define SUNXI_INPUT_CLOCK		24000000	/* 24 MHz */
+#define SUN4I_SPI_MAX_RATE		SUNXI_INPUT_CLOCK
+#endif
 #define SUN4I_SPI_MIN_RATE		3000
 #define SUN4I_SPI_DEFAULT_RATE		1000000
-#define SUN4I_SPI_TIMEOUT_US		1000000
+#define SUN4I_SPI_TIMEOUT_MS		1000
 
 #define SPI_REG(priv, reg)		((priv)->base + \
 					(priv)->variant->regs[reg])
@@ -221,6 +229,60 @@ err_ahb:
 	return ret;
 }
 
+static void sun4i_spi_set_speed_mode(struct udevice *dev)
+{
+	struct sun4i_spi_priv *priv = dev_get_priv(dev);
+	unsigned int div;
+	u32 reg;
+
+	/*
+	 * Setup clock divider.
+	 *
+	 * We have two choices there. Either we can use the clock
+	 * divide rate 1, which is calculated thanks to this formula:
+	 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
+	 * Or we can use CDR2, which is calculated with the formula:
+	 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
+	 * Whether we use the former or the latter is set through the
+	 * DRS bit.
+	 *
+	 * First try CDR2, and if we can't reach the expected
+	 * frequency, fall back to CDR1.
+	 */
+
+	div = DIV_ROUND_UP(SUNXI_INPUT_CLOCK, priv->freq);
+	reg = readl(SPI_REG(priv, SPI_CCR));
+
+	if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
+		div /= 2;
+		if (div > 0)
+			div--;
+
+		reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
+		reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
+	} else {
+		div = fls(div - 1);
+		/* The F1C100s encodes the divider as 2^(n+1) */
+		if (IS_ENABLED(CONFIG_MACH_SUNIV))
+			div--;
+		reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
+		reg |= SUN4I_CLK_CTL_CDR1(div);
+	}
+
+	writel(reg, SPI_REG(priv, SPI_CCR));
+
+	reg = readl(SPI_REG(priv, SPI_TCR));
+	reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
+
+	if (priv->mode & SPI_CPOL)
+		reg |= SPI_BIT(priv, SPI_TCR_CPOL);
+
+	if (priv->mode & SPI_CPHA)
+		reg |= SPI_BIT(priv, SPI_TCR_CPHA);
+
+	writel(reg, SPI_REG(priv, SPI_TCR));
+}
+
 static int sun4i_spi_claim_bus(struct udevice *dev)
 {
 	struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
@@ -240,6 +302,8 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
 	setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
 		     SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
 
+	sun4i_spi_set_speed_mode(dev->parent);
+
 	return 0;
 }
 
@@ -262,7 +326,6 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
 
 	u32 len = bitlen / 8;
-	u32 rx_fifocnt;
 	u8 nbytes;
 	int ret;
 
@@ -300,13 +363,10 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
 		setbits_le32(SPI_REG(priv, SPI_TCR),
 			     SPI_BIT(priv, SPI_TCR_XCH));
 
-		/* Wait till RX FIFO to be empty */
-		ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
-					 rx_fifocnt,
-					 (((rx_fifocnt &
-					 SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >>
-					 SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
-					 SUN4I_SPI_TIMEOUT_US);
+		/* Wait for the transfer to be done */
+		ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR),
+					SPI_BIT(priv, SPI_TCR_XCH),
+					false, SUN4I_SPI_TIMEOUT_MS, false);
 		if (ret < 0) {
 			printf("ERROR: sun4i_spi: Timeout transferring data\n");
 			sun4i_spi_set_cs(bus, slave_plat->cs, false);
@@ -329,46 +389,14 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
 {
 	struct sun4i_spi_plat *plat = dev_get_plat(dev);
 	struct sun4i_spi_priv *priv = dev_get_priv(dev);
-	unsigned int div;
-	u32 reg;
 
 	if (speed > plat->max_hz)
 		speed = plat->max_hz;
 
 	if (speed < SUN4I_SPI_MIN_RATE)
 		speed = SUN4I_SPI_MIN_RATE;
-	/*
-	 * Setup clock divider.
-	 *
-	 * We have two choices there. Either we can use the clock
-	 * divide rate 1, which is calculated thanks to this formula:
-	 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
-	 * Or we can use CDR2, which is calculated with the formula:
-	 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-	 * Whether we use the former or the latter is set through the
-	 * DRS bit.
-	 *
-	 * First try CDR2, and if we can't reach the expected
-	 * frequency, fall back to CDR1.
-	 */
-
-	div = SUN4I_SPI_MAX_RATE / (2 * speed);
-	reg = readl(SPI_REG(priv, SPI_CCR));
-
-	if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
-		if (div > 0)
-			div--;
-
-		reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
-		reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
-	} else {
-		div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
-		reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
-		reg |= SUN4I_CLK_CTL_CDR1(div);
-	}
 
 	priv->freq = speed;
-	writel(reg, SPI_REG(priv, SPI_CCR));
 
 	return 0;
 }
@@ -376,19 +404,8 @@ static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
 static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
 {
 	struct sun4i_spi_priv *priv = dev_get_priv(dev);
-	u32 reg;
-
-	reg = readl(SPI_REG(priv, SPI_TCR));
-	reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
-
-	if (mode & SPI_CPOL)
-		reg |= SPI_BIT(priv, SPI_TCR_CPOL);
-
-	if (mode & SPI_CPHA)
-		reg |= SPI_BIT(priv, SPI_TCR_CPHA);
 
 	priv->mode = mode;
-	writel(reg, SPI_REG(priv, SPI_TCR));
 
 	return 0;
 }

--- a/include/clk/sunxi.h
+++ b/include/clk/sunxi.h
@@ -70,34 +70,21 @@ struct ccu_reset {
 struct ccu_desc {
 	const struct ccu_clk_gate *gates;
 	const struct ccu_reset *resets;
+	u8 num_gates;
+	u8 num_resets;
 };
 
 /**
- * struct ccu_priv - sunxi clock control unit
+ * struct ccu_plat - sunxi clock control unit platform data
  *
  * @base:	base address
  * @desc:	ccu descriptor
  */
-struct ccu_priv {
+struct ccu_plat {
 	void *base;
 	const struct ccu_desc *desc;
 };
 
-/**
- * sunxi_clk_probe - common sunxi clock probe
- * @dev:	clock device
- */
-int sunxi_clk_probe(struct udevice *dev);
-
 extern struct clk_ops sunxi_clk_ops;
 
-/**
- * sunxi_reset_bind() - reset binding
- *
- * @dev:       reset device
- * @count:     reset count
- * Return: 0 success, or error value
- */
-int sunxi_reset_bind(struct udevice *dev, ulong count);
-
 #endif /* _CLK_SUNXI_H */

--- a/include/configs/sun4i.h
+++ b/include/configs/sun4i.h
@@ -2,18 +2,12 @@
 /*
  * (C) Copyright 2012-2013 Henrik Nordstrom <[e-mail]>
  *
- * Configuration settings for the Allwinner A10 (sun4i) CPU
+ * Placeholder wrapper to allow addressing Allwinner A10 (sun4i) CPU
+ * based devices separately. Please do not add anything in here.
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * A10 specific configuration
- */
-
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */

--- a/include/configs/sun50i.h
+++ b/include/configs/sun50i.h
@@ -1,26 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Configuration settings for the Allwinner A64 (sun50i) CPU
+ * Placeholder wrapper to allow addressing Allwinner A64 (and later) sun50i
+ * CPU based devices separately. Please do not add anything in here.
  */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * A64 specific configuration
- */
-
-#ifndef CONFIG_SUN50I_GEN_H6
-#define GICD_BASE		0x1c81000
-#define GICC_BASE		0x1c82000
-#else
-#define GICD_BASE		0x3021000
-#define GICC_BASE		0x3022000
-#endif
-
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */

--- a/include/configs/sun5i.h
+++ b/include/configs/sun5i.h
@@ -2,18 +2,12 @@
 /*
  * (C) Copyright 2012-2013 Henrik Nordstrom <[e-mail]>
  *
- * Configuration settings for the Allwinner A13 (sun5i) CPU
+ * Placeholder wrapper to allow addressing Allwinner A13 (sun5i) CPU
+ * based devices separately. Please do not add anything in here.
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * High Level Configuration Options
- */
-
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */

--- a/include/configs/sun6i.h
+++ b/include/configs/sun6i.h
@@ -4,15 +4,12 @@
  * (C) Copyright 2013 Luke Kenneth Casson Leighton <[e-mail]>
  * (C) Copyright 2013 Maxime Ripard <[e-mail]>
  *
- * Configuration settings for the Allwinner A31 (sun6i) CPU
+ * Placeholder wrapper to allow addressing Allwinner A31 (sun6i) CPU
+ * based devices separately. Please do not add anything in here.
  */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */

--- a/include/configs/sun7i.h
+++ b/include/configs/sun7i.h
@@ -3,14 +3,12 @@
  * (C) Copyright 2012-2013 Henrik Nordstrom <[e-mail]>
  * (C) Copyright 2013 Luke Kenneth Casson Leighton <[e-mail]>
  *
- * Configuration settings for the Allwinner A20 (sun7i) CPU
+ * Placeholder wrapper to allow addressing Allwinner A20 (sun7i) CPU
+ * based devices separately. Please do not add anything in here.
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */

--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -2,21 +2,12 @@
 /*
  * (C) Copyright 2014 Chen-Yu Tsai <[e-mail]>
  *
- * Configuration settings for the Allwinner A23 (sun8i) CPU
+ * Placeholder wrapper to allow addressing Allwinner A23 (and later) sun8i
+ * CPU based devices separately. Please do not add anything in here.
  */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * A23 specific configuration
- */
-
-#include <asm/arch/cpu.h>
-
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */

--- a/include/configs/sun9i.h
+++ b/include/configs/sun9i.h
@@ -2,19 +2,12 @@
 /*
  * (C) Copyright 2015 Hans de Goede <[e-mail]>
  *
- * Configuration settings for the Allwinner A80 (sun9i) CPU
+ * Placeholder wrapper to allow addressing Allwinner A80 (sun9i) CPU
+ * based devices separately. Please do not add anything in here.
  */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * A80 specific configuration
- */
-
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */

--- a/include/configs/suniv.h
+++ b/include/configs/suniv.h
@@ -1,14 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Configuration settings for new Allwinner F-series (suniv) CPU
+ * Placeholder wrapper to allow addressing Allwinner F-series (suniv) CPU
+ * based devices separately. Please do not add anything in here.
  */
-
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-/*
- * Include common sunxi configuration where most the settings are
- */
 #include <configs/sunxi-common.h>
 
 #endif /* __CONFIG_H */