GNU Binutils with patches for OS216
Revisión | 026122a670440bc51266f8e013e5c5877c19b54e (tree) |
---|---|
Tiempo | 2016-06-04 08:38:02 |
Autor | Peter Bergner <bergner@vnet...> |
Commiter | Peter Bergner |
Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
opcodes/
PR binutils/20196
* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
opcodes for E6500.
gas/
PR binutils/20196
* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
stbcx., sthcx., stwcx., stdcx.>: Add tests.
* gas/testsuite/gas/ppc/e6500.d: Likewise.
* gas/testsuite/gas/ppc/power8.s: Likewise.
* gas/testsuite/gas/ppc/power8.d: Likewise.
* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
stdcx.>: Add tests.
* gas/testsuite/gas/ppc/power4.d: Likewise.
@@ -1,3 +1,15 @@ | ||
1 | +2016-06-03 Peter Bergner <bergner@vnet.ibm.com> | |
2 | + | |
3 | + PR binutils/20196 | |
4 | + * gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx, | |
5 | + stbcx., sthcx., stwcx., stdcx.>: Add tests. | |
6 | + * gas/testsuite/gas/ppc/e6500.d: Likewise. | |
7 | + * gas/testsuite/gas/ppc/power8.s: Likewise. | |
8 | + * gas/testsuite/gas/ppc/power8.d: Likewise. | |
9 | + * gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx., | |
10 | + stdcx.>: Add tests. | |
11 | + * gas/testsuite/gas/ppc/power4.d: Likewise. | |
12 | + | |
1 | 13 | 2016-06-03 H.J. Lu <hongjiu.lu@intel.com> |
2 | 14 | |
3 | 15 | PR binutis/18386 |
@@ -73,3 +73,20 @@ Disassembly of section \.text: | ||
73 | 73 | fc: (7c 43 09 8d|8d 09 43 7c) icblq. 2,r3,r1 |
74 | 74 | 100: (7c 10 02 dc|dc 02 10 7c) mftmr r0,16 |
75 | 75 | 104: (7c 10 03 dc|dc 03 10 7c) mttmr 16,r0 |
76 | +.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7 | |
77 | +.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7 | |
78 | +.*: (7e a0 40 e8|e8 40 a0 7e) lharx r21,0,r8 | |
79 | +.*: (7e a1 40 e8|e8 40 a1 7e) lharx r21,r1,r8 | |
80 | +.*: (7e c0 48 28|28 48 c0 7e) lwarx r22,0,r9 | |
81 | +.*: (7e c1 48 28|28 48 c1 7e) lwarx r22,r1,r9 | |
82 | +.*: (7e e0 50 a8|a8 50 e0 7e) ldarx r23,0,r10 | |
83 | +.*: (7e e1 50 a8|a8 50 e1 7e) ldarx r23,r1,r10 | |
84 | +.*: (7d 40 3d 6d|6d 3d 40 7d) stbcx\. r10,0,r7 | |
85 | +.*: (7d 41 3d 6d|6d 3d 41 7d) stbcx\. r10,r1,r7 | |
86 | +.*: (7d 60 45 ad|ad 45 60 7d) sthcx\. r11,0,r8 | |
87 | +.*: (7d 61 45 ad|ad 45 61 7d) sthcx\. r11,r1,r8 | |
88 | +.*: (7d 80 49 2d|2d 49 80 7d) stwcx\. r12,0,r9 | |
89 | +.*: (7d 81 49 2d|2d 49 81 7d) stwcx\. r12,r1,r9 | |
90 | +.*: (7d a0 51 ad|ad 51 a0 7d) stdcx\. r13,0,r10 | |
91 | +.*: (7d a1 51 ad|ad 51 a1 7d) stdcx\. r13,r1,r10 | |
92 | +#pass |
@@ -67,3 +67,19 @@ start: | ||
67 | 67 | icblq. 2,3,1 |
68 | 68 | mftmr 0,16 |
69 | 69 | mttmr 16,0 |
70 | + lbarx 20,0,7 | |
71 | + lbarx 20,1,7 | |
72 | + lharx 21,0,8 | |
73 | + lharx 21,1,8 | |
74 | + lwarx 22,0,9 | |
75 | + lwarx 22,1,9 | |
76 | + ldarx 23,0,10 | |
77 | + ldarx 23,1,10 | |
78 | + stbcx. 10,0,7 | |
79 | + stbcx. 10,1,7 | |
80 | + sthcx. 11,0,8 | |
81 | + sthcx. 11,1,8 | |
82 | + stwcx. 12,0,9 | |
83 | + stwcx. 12,1,9 | |
84 | + stdcx. 13,0,10 | |
85 | + stdcx. 13,1,10 |
@@ -10,7 +10,7 @@ start address 0x0+ | ||
10 | 10 | |
11 | 11 | Sections: |
12 | 12 | Idx Name +Size +VMA +LMA +File off +Algn |
13 | - +0 \.text +0+e8 +0+ +0+ +.* | |
13 | + +0 \.text +0+108 +0+ +0+ +.* | |
14 | 14 | +CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE |
15 | 15 | +1 \.data +0+20 +0+ +0+ +.* |
16 | 16 | +CONTENTS, ALLOC, LOAD, DATA |
@@ -106,3 +106,12 @@ Disassembly of section \.text: | ||
106 | 106 | .*: (7c 20 04 ac|ac 04 20 7c) lwsync |
107 | 107 | .*: (7c 40 04 ac|ac 04 40 7c) ptesync |
108 | 108 | .*: (7c 40 04 ac|ac 04 40 7c) ptesync |
109 | +.*: (7e 80 30 28|28 30 80 7e) lwarx r20,0,r6 | |
110 | +.*: (7e 81 30 28|28 30 81 7e) lwarx r20,r1,r6 | |
111 | +.*: (7e a0 38 a8|a8 38 a0 7e) ldarx r21,0,r7 | |
112 | +.*: (7e a1 38 a8|a8 38 a1 7e) ldarx r21,r1,r7 | |
113 | +.*: (7e c0 41 2d|2d 41 c0 7e) stwcx\. r22,0,r8 | |
114 | +.*: (7e c1 41 2d|2d 41 c1 7e) stwcx\. r22,r1,r8 | |
115 | +.*: (7e e0 49 ad|ad 49 e0 7e) stdcx\. r23,0,r9 | |
116 | +.*: (7e e1 49 ad|ad 49 e1 7e) stdcx\. r23,r1,r9 | |
117 | +#pass |
@@ -79,6 +79,14 @@ dsym1: | ||
79 | 79 | sync 1 |
80 | 80 | ptesync |
81 | 81 | sync 2 |
82 | + lwarx 20,0,6 | |
83 | + lwarx 20,1,6 | |
84 | + ldarx 21,0,7 | |
85 | + ldarx 21,1,7 | |
86 | + stwcx. 22,0,8 | |
87 | + stwcx. 22,1,8 | |
88 | + stdcx. 23,0,9 | |
89 | + stdcx. 23,1,9 | |
82 | 90 | |
83 | 91 | .section ".data" |
84 | 92 | usym0: .llong 0xcafebabe |
@@ -160,4 +160,36 @@ Disassembly of section \.text: | ||
160 | 160 | .*: (7d 20 3f 99|99 3f 20 7d) stxvd2x vs41,0,r7 |
161 | 161 | .*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8 |
162 | 162 | .*: (7d 75 47 98|98 47 75 7d) stxvd2x vs11,r21,r8 |
163 | +.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7 | |
164 | +.*: (7e 80 38 68|68 38 80 7e) lbarx r20,0,r7 | |
165 | +.*: (7e 80 38 69|69 38 80 7e) lbarx r20,0,r7,1 | |
166 | +.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7 | |
167 | +.*: (7e 81 38 68|68 38 81 7e) lbarx r20,r1,r7 | |
168 | +.*: (7e 81 38 69|69 38 81 7e) lbarx r20,r1,r7,1 | |
169 | +.*: (7e a0 40 a8|a8 40 a0 7e) ldarx r21,0,r8 | |
170 | +.*: (7e a0 40 a8|a8 40 a0 7e) ldarx r21,0,r8 | |
171 | +.*: (7e a0 40 a9|a9 40 a0 7e) ldarx r21,0,r8,1 | |
172 | +.*: (7e a1 40 a8|a8 40 a1 7e) ldarx r21,r1,r8 | |
173 | +.*: (7e a1 40 a8|a8 40 a1 7e) ldarx r21,r1,r8 | |
174 | +.*: (7e a1 40 a9|a9 40 a1 7e) ldarx r21,r1,r8,1 | |
175 | +.*: (7e c0 48 e8|e8 48 c0 7e) lharx r22,0,r9 | |
176 | +.*: (7e c0 48 e8|e8 48 c0 7e) lharx r22,0,r9 | |
177 | +.*: (7e c0 48 e9|e9 48 c0 7e) lharx r22,0,r9,1 | |
178 | +.*: (7e c1 48 e8|e8 48 c1 7e) lharx r22,r1,r9 | |
179 | +.*: (7e c1 48 e8|e8 48 c1 7e) lharx r22,r1,r9 | |
180 | +.*: (7e c1 48 e9|e9 48 c1 7e) lharx r22,r1,r9,1 | |
181 | +.*: (7e e0 50 28|28 50 e0 7e) lwarx r23,0,r10 | |
182 | +.*: (7e e0 50 28|28 50 e0 7e) lwarx r23,0,r10 | |
183 | +.*: (7e e0 50 29|29 50 e0 7e) lwarx r23,0,r10,1 | |
184 | +.*: (7e e1 50 28|28 50 e1 7e) lwarx r23,r1,r10 | |
185 | +.*: (7e e1 50 28|28 50 e1 7e) lwarx r23,r1,r10 | |
186 | +.*: (7e e1 50 29|29 50 e1 7e) lwarx r23,r1,r10,1 | |
187 | +.*: (7d 40 3d 6d|6d 3d 40 7d) stbcx\. r10,0,r7 | |
188 | +.*: (7d 41 3d 6d|6d 3d 41 7d) stbcx\. r10,r1,r7 | |
189 | +.*: (7d 60 45 ad|ad 45 60 7d) sthcx\. r11,0,r8 | |
190 | +.*: (7d 61 45 ad|ad 45 61 7d) sthcx\. r11,r1,r8 | |
191 | +.*: (7d 80 49 2d|2d 49 80 7d) stwcx\. r12,0,r9 | |
192 | +.*: (7d 81 49 2d|2d 49 81 7d) stwcx\. r12,r1,r9 | |
193 | +.*: (7d a0 51 ad|ad 51 a0 7d) stdcx\. r13,0,r10 | |
194 | +.*: (7d a1 51 ad|ad 51 a1 7d) stdcx\. r13,r1,r10 | |
163 | 195 | #pass |
@@ -152,3 +152,35 @@ power8: | ||
152 | 152 | stxvd2x 41,0,7 |
153 | 153 | stxvx 11,21,8 |
154 | 154 | stxvd2x 11,21,8 |
155 | + lbarx 20,0,7 | |
156 | + lbarx 20,0,7,0 | |
157 | + lbarx 20,0,7,1 | |
158 | + lbarx 20,1,7 | |
159 | + lbarx 20,1,7,0 | |
160 | + lbarx 20,1,7,1 | |
161 | + ldarx 21,0,8 | |
162 | + ldarx 21,0,8,0 | |
163 | + ldarx 21,0,8,1 | |
164 | + ldarx 21,1,8 | |
165 | + ldarx 21,1,8,0 | |
166 | + ldarx 21,1,8,1 | |
167 | + lharx 22,0,9 | |
168 | + lharx 22,0,9,0 | |
169 | + lharx 22,0,9,1 | |
170 | + lharx 22,1,9 | |
171 | + lharx 22,1,9,0 | |
172 | + lharx 22,1,9,1 | |
173 | + lwarx 23,0,10 | |
174 | + lwarx 23,0,10,0 | |
175 | + lwarx 23,0,10,1 | |
176 | + lwarx 23,1,10 | |
177 | + lwarx 23,1,10,0 | |
178 | + lwarx 23,1,10,1 | |
179 | + stbcx. 10,0,7 | |
180 | + stbcx. 10,1,7 | |
181 | + sthcx. 11,0,8 | |
182 | + sthcx. 11,1,8 | |
183 | + stwcx. 12,0,9 | |
184 | + stwcx. 12,1,9 | |
185 | + stdcx. 13,0,10 | |
186 | + stdcx. 13,1,10 |
@@ -1,3 +1,9 @@ | ||
1 | +2016-06-03 Peter Bergner <bergner@vnet.ibm.com> | |
2 | + | |
3 | + PR binutils/20196 | |
4 | + * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable | |
5 | + opcodes for E6500. | |
6 | + | |
1 | 7 | 2016-06-03 H.J. Lu <hongjiu.lu@intel.com> |
2 | 8 | |
3 | 9 | PR binutis/18386 |
@@ -4824,7 +4824,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { | ||
4824 | 4824 | {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, |
4825 | 4825 | {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}}, |
4826 | 4826 | |
4827 | -{"lbarx", X(31,52), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, | |
4827 | +{"lbarx", X(31,52), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, | |
4828 | 4828 | |
4829 | 4829 | {"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, |
4830 | 4830 |
@@ -4904,7 +4904,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { | ||
4904 | 4904 | {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}}, |
4905 | 4905 | {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}}, |
4906 | 4906 | |
4907 | -{"lharx", X(31,116), XEH_MASK, POWER8|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, | |
4907 | +{"lharx", X(31,116), XEH_MASK, POWER8|E6500|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, | |
4908 | 4908 | |
4909 | 4909 | {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, |
4910 | 4910 |
@@ -5954,7 +5954,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { | ||
5954 | 5954 | {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}}, |
5955 | 5955 | {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}}, |
5956 | 5956 | |
5957 | -{"stbcx.", XRC(31,694,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, | |
5957 | +{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}}, | |
5958 | 5958 | |
5959 | 5959 | {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, |
5960 | 5960 |
@@ -5986,7 +5986,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { | ||
5986 | 5986 | {"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}}, |
5987 | 5987 | {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, |
5988 | 5988 | |
5989 | -{"sthcx.", XRC(31,726,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, | |
5989 | +{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, PPCNONE, {RS, RA0, RB}}, | |
5990 | 5990 | |
5991 | 5991 | {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, |
5992 | 5992 |