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Revisión	a5f580e51a77f278b66e87d7d1784225aae51cbf (tree)
Tiempo	2018-09-13 18:11:26
Autor	Jan Beulich <jbeulich@nove...>
Commiter	Jan Beulich

Log Message

x86: drop bogus IgnoreSize from SSE insns

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Diferencia incremental

--- a/opcodes/ChangeLog

+++ b/opcodes/ChangeLog

		@@ -1,5 +1,10 @@
1	1	2018-09-13 Jan Beulich <jbeulich@suse.com>
2	2
	3	+ * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
	4	+ * i386-tbl.h: Re-generate.
	5	+
	6	+2018-09-13 Jan Beulich <jbeulich@suse.com>
	7	+
3	8	* i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
4	9	(vpbroadcastw, rdpid): Drop NoRex64.
5	10	* i386-tbl.h: Re-generate.

--- a/opcodes/i386-opc.tbl

+++ b/opcodes/i386-opc.tbl

		@@ -1135,48 +1135,48 @@ pxor, 2, 0xfef, None, 2, CpuMMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu
1135	1135
1136	1136	// SSE instructions.
1137	1137
1138		-addps, 2, 0x58, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1139		-addps, 2, 0xf58, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1138	+addps, 2, 0x58, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1139	+addps, 2, 0xf58, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1140	1140	addss, 2, 0xf358, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1141	1141	addss, 2, 0xf30f58, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1142		-andnps, 2, 0x55, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1143		-andnps, 2, 0xf55, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1144		-andps, 2, 0x54, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1145		-andps, 2, 0xf54, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1146		-cmpeqps, 2, 0xc2, 0x0, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1147		-cmpeqps, 2, 0xfc2, 0x0, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1142	+andnps, 2, 0x55, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1143	+andnps, 2, 0xf55, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1144	+andps, 2, 0x54, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1145	+andps, 2, 0xf54, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1146	+cmpeqps, 2, 0xc2, 0x0, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1147	+cmpeqps, 2, 0xfc2, 0x0, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1148	1148	cmpeqss, 2, 0xf3c2, 0x0, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1149	1149	cmpeqss, 2, 0xf30fc2, 0x0, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1150		-cmpleps, 2, 0xc2, 0x2, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1151		-cmpleps, 2, 0xfc2, 0x2, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1150	+cmpleps, 2, 0xc2, 0x2, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1151	+cmpleps, 2, 0xfc2, 0x2, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1152	1152	cmpless, 2, 0xf3c2, 0x2, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1153	1153	cmpless, 2, 0xf30fc2, 0x2, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1154		-cmpltps, 2, 0xc2, 0x1, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1155		-cmpltps, 2, 0xfc2, 0x1, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1154	+cmpltps, 2, 0xc2, 0x1, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1155	+cmpltps, 2, 0xfc2, 0x1, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1156	1156	cmpltss, 2, 0xf3c2, 0x1, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1157	1157	cmpltss, 2, 0xf30fc2, 0x1, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1158		-cmpneqps, 2, 0xc2, 0x4, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1159		-cmpneqps, 2, 0xfc2, 0x4, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1158	+cmpneqps, 2, 0xc2, 0x4, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1159	+cmpneqps, 2, 0xfc2, 0x4, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1160	1160	cmpneqss, 2, 0xf3c2, 0x4, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1161	1161	cmpneqss, 2, 0xf30fc2, 0x4, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1162		-cmpnleps, 2, 0xc2, 0x6, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1163		-cmpnleps, 2, 0xfc2, 0x6, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1162	+cmpnleps, 2, 0xc2, 0x6, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1163	+cmpnleps, 2, 0xfc2, 0x6, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1164	1164	cmpnless, 2, 0xf3c2, 0x6, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1165	1165	cmpnless, 2, 0xf30fc2, 0x6, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1166		-cmpnltps, 2, 0xc2, 0x5, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1167		-cmpnltps, 2, 0xfc2, 0x5, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1166	+cmpnltps, 2, 0xc2, 0x5, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1167	+cmpnltps, 2, 0xfc2, 0x5, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1168	1168	cmpnltss, 2, 0xf3c2, 0x5, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1169	1169	cmpnltss, 2, 0xf30fc2, 0x5, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1170		-cmpordps, 2, 0xc2, 0x7, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1171		-cmpordps, 2, 0xfc2, 0x7, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1170	+cmpordps, 2, 0xc2, 0x7, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1171	+cmpordps, 2, 0xfc2, 0x7, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1172	1172	cmpordss, 2, 0xf3c2, 0x7, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1173	1173	cmpordss, 2, 0xf30fc2, 0x7, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1174		-cmpunordps, 2, 0xc2, 0x3, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1175		-cmpunordps, 2, 0xfc2, 0x3, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1174	+cmpunordps, 2, 0xc2, 0x3, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1175	+cmpunordps, 2, 0xfc2, 0x3, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1176	1176	cmpunordss, 2, 0xf3c2, 0x3, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1177	1177	cmpunordss, 2, 0xf30fc2, 0x3, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1178		-cmpps, 3, 0xc2, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1179		-cmpps, 3, 0xfc2, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1178	+cmpps, 3, 0xc2, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1179	+cmpps, 3, 0xfc2, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, RegXMM\|Unspecified\|BaseIndex, RegXMM }
1180	1180	cmpss, 3, 0xf3c2, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1181	1181	cmpss, 3, 0xf30fc2, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1182	1182	comiss, 2, 0x2f, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }

		@@ -1192,37 +1192,37 @@ cvtss2si, 2, 0xf30f2d, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_sSuf
1192	1192	cvttps2pi, 2, 0xf2c, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { Qword\|Unspecified\|BaseIndex\|RegXMM, RegMMX }
1193	1193	cvttss2si, 2, 0xf32c, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|IgnoreSize\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|ToQword\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, Reg32\|Reg64 }
1194	1194	cvttss2si, 2, 0xf30f2c, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|ToQword, { Dword\|Unspecified\|BaseIndex\|RegXMM, Reg32\|Reg64 }
1195		-divps, 2, 0x5e, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1196		-divps, 2, 0xf5e, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1195	+divps, 2, 0x5e, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1196	+divps, 2, 0xf5e, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1197	1197	divss, 2, 0xf35e, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1198	1198	divss, 2, 0xf30f5e, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1199	1199	ldmxcsr, 1, 0xae, 0x2, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex }
1200	1200	ldmxcsr, 1, 0xfae, 0x2, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { Dword\|Unspecified\|BaseIndex }
1201		-maskmovq, 2, 0xff7, None, 2, CpuSSE\|Cpu3dnowA, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { RegMMX, RegMMX }
1202		-maxps, 2, 0x5f, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1203		-maxps, 2, 0xf5f, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1201	+maskmovq, 2, 0xff7, None, 2, CpuSSE\|Cpu3dnowA, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { RegMMX, RegMMX }
	1202	+maxps, 2, 0x5f, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1203	+maxps, 2, 0xf5f, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1204	1204	maxss, 2, 0xf35f, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1205	1205	maxss, 2, 0xf30f5f, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1206		-minps, 2, 0x5d, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1207		-minps, 2, 0xf5d, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1206	+minps, 2, 0x5d, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1207	+minps, 2, 0xf5d, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1208	1208	minss, 2, 0xf35d, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1209	1209	minss, 2, 0xf30f5d, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1210	1210	movaps, 2, 0x28, None, 1, CpuAVX, D\|Modrm\|Vex\|VexOpcode=0\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1211	1211	movaps, 2, 0xf28, None, 2, CpuSSE, D\|Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1212		-movhlps, 2, 0x12, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, RegXMM }
1213		-movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }
	1212	+movhlps, 2, 0x12, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, RegXMM }
	1213	+movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }
1214	1214	movhps, 2, 0x16, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecified\|BaseIndex, RegXMM }
1215	1215	movhps, 2, 0x17, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Qword\|Unspecified\|BaseIndex }
1216	1216	movhps, 2, 0xf16, None, 2, CpuSSE, D\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex, RegXMM }
1217		-movlhps, 2, 0x16, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, RegXMM }
1218		-movlhps, 2, 0xf16, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }
	1217	+movlhps, 2, 0x16, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, RegXMM }
	1218	+movlhps, 2, 0xf16, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }
1219	1219	movlps, 2, 0x12, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecified\|BaseIndex, RegXMM }
1220	1220	movlps, 2, 0x13, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Qword\|Unspecified\|BaseIndex }
1221	1221	movlps, 2, 0xf12, None, 2, CpuSSE, D\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex, RegXMM }
1222		-movmskps, 2, 0x50, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { RegXMM, Reg32\|Reg64 }
1223		-movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|NoRex64, { RegXMM, Reg32\|Reg64 }
1224		-movntps, 2, 0x2b, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Xmmword\|Unspecified\|BaseIndex }
1225		-movntps, 2, 0xf2b, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Xmmword\|Unspecified\|BaseIndex }
	1222	+movmskps, 2, 0x50, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { RegXMM, Reg32\|Reg64 }
	1223	+movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|NoRex64, { RegXMM, Reg32\|Reg64 }
	1224	+movntps, 2, 0x2b, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Xmmword\|Unspecified\|BaseIndex }
	1225	+movntps, 2, 0xf2b, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Xmmword\|Unspecified\|BaseIndex }
1226	1226	movntq, 2, 0xfe7, None, 2, CpuSSE\|Cpu3dnowA, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { RegMMX, Qword\|Unspecified\|BaseIndex }
1227	1227	movntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Xmmword\|Unspecified\|BaseIndex }
1228	1228	movntdq, 2, 0x660fe7, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Xmmword\|Unspecified\|BaseIndex }

		@@ -1231,12 +1231,12 @@ movss, 2, 0xf310, None, 1, CpuAVX, D\|Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No
1231	1231	movss, 2, 0xf30f10, None, 2, CpuSSE, D\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1232	1232	movups, 2, 0x10, None, 1, CpuAVX, D\|Modrm\|Vex\|VexOpcode=0\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1233	1233	movups, 2, 0xf10, None, 2, CpuSSE, D\|Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1234		-mulps, 2, 0x59, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1235		-mulps, 2, 0xf59, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1234	+mulps, 2, 0x59, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1235	+mulps, 2, 0xf59, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1236	1236	mulss, 2, 0xf359, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1237	1237	mulss, 2, 0xf30f59, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1238		-orps, 2, 0x56, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1239		-orps, 2, 0xf56, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1238	+orps, 2, 0x56, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1239	+orps, 2, 0xf56, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1240	1240	pavgb, 2, 0xfe0, None, 2, CpuSSE\|Cpu3dnowA, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { Qword\|Unspecified\|BaseIndex\|RegMMX, RegMMX }
1241	1241	pavgb, 2, 0x66e0, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1242	1242	pavgb, 2, 0x660fe0, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }

		@@ -1282,35 +1282,35 @@ psadbw, 2, 0xff6, None, 2, CpuSSE\|Cpu3dnowA, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No
1282	1282	psadbw, 2, 0x66f6, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1283	1283	psadbw, 2, 0x660ff6, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1284	1284	pshufw, 3, 0xf70, None, 2, CpuSSE\|Cpu3dnowA, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { Imm8, Qword\|Unspecified\|BaseIndex\|RegMMX, RegMMX }
1285		-rcpps, 2, 0x53, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1286		-rcpps, 2, 0xf53, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1285	+rcpps, 2, 0x53, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1286	+rcpps, 2, 0xf53, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1287	1287	rcpss, 2, 0xf353, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1288	1288	rcpss, 2, 0xf30f53, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1289		-rsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1290		-rsqrtps, 2, 0xf52, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1289	+rsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1290	+rsqrtps, 2, 0xf52, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1291	1291	rsqrtss, 2, 0xf352, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1292	1292	rsqrtss, 2, 0xf30f52, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1293	1293	sfence, 0, 0xfae, 0xf8, 2, CpuSSE\|Cpu3dnowA, IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|NoAVX, { 0 }
1294		-shufps, 3, 0xc6, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1295		-shufps, 3, 0xfc6, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1296		-sqrtps, 2, 0x51, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1297		-sqrtps, 2, 0xf51, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1294	+shufps, 3, 0xc6, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1295	+shufps, 3, 0xfc6, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1296	+sqrtps, 2, 0x51, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1297	+sqrtps, 2, 0xf51, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1298	1298	sqrtss, 2, 0xf351, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1299	1299	sqrtss, 2, 0xf30f51, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1300	1300	stmxcsr, 1, 0xae, 0x3, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex }
1301	1301	stmxcsr, 1, 0xfae, 0x3, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { Dword\|Unspecified\|BaseIndex }
1302		-subps, 2, 0x5c, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1303		-subps, 2, 0xf5c, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1302	+subps, 2, 0x5c, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1303	+subps, 2, 0xf5c, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1304	1304	subss, 2, 0xf35c, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1305	1305	subss, 2, 0xf30f5c, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1306	1306	ucomiss, 2, 0x2e, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1307	1307	ucomiss, 2, 0xf2e, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1308		-unpckhps, 2, 0x15, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1309		-unpckhps, 2, 0xf15, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1310		-unpcklps, 2, 0x14, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1311		-unpcklps, 2, 0xf14, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1312		-xorps, 2, 0x57, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
1313		-xorps, 2, 0xf57, None, 2, CpuSSE, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|RegXMM, RegXMM }
	1308	+unpckhps, 2, 0x15, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1309	+unpckhps, 2, 0xf15, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1310	+unpcklps, 2, 0x14, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1311	+unpcklps, 2, 0xf14, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1312	+xorps, 2, 0x57, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
	1313	+xorps, 2, 0xf57, None, 2, CpuSSE, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM\|Unspecified\|BaseIndex, RegXMM }
1314	1314
1315	1315	// SSE2 instructions.
1316	1316

--- a/opcodes/i386-tbl.h

+++ b/opcodes/i386-tbl.h

		@@ -13626,7 +13626,7 @@ const insn_template i386_optab[] =
13626	13626	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13627	13627	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13628	13628	0, 0, 0, 0, 0, 0 } },
13629		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13629	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13630	13630	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13631	13631	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13632	13632	0, 0 },

		@@ -13643,7 +13643,7 @@ const insn_template i386_optab[] =
13643	13643	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13644	13644	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13645	13645	0, 0, 0, 0, 0, 0 } },
13646		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13646	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13647	13647	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13648	13648	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13649	13649	0, 0 },

		@@ -13694,7 +13694,7 @@ const insn_template i386_optab[] =
13694	13694	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13695	13695	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13696	13696	0, 0, 0, 0, 0, 0 } },
13697		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13697	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13698	13698	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13699	13699	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13700	13700	0, 0 },

		@@ -13711,7 +13711,7 @@ const insn_template i386_optab[] =
13711	13711	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13712	13712	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13713	13713	0, 0, 0, 0, 0, 0 } },
13714		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13714	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13715	13715	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13716	13716	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13717	13717	0, 0 },

		@@ -13728,7 +13728,7 @@ const insn_template i386_optab[] =
13728	13728	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13729	13729	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13730	13730	0, 0, 0, 0, 0, 0 } },
13731		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13731	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13732	13732	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13733	13733	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13734	13734	0, 0 },

		@@ -13745,7 +13745,7 @@ const insn_template i386_optab[] =
13745	13745	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13746	13746	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13747	13747	0, 0, 0, 0, 0, 0 } },
13748		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13748	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13749	13749	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13750	13750	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13751	13751	0, 0 },

		@@ -13762,7 +13762,7 @@ const insn_template i386_optab[] =
13762	13762	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13763	13763	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13764	13764	0, 0, 0, 0, 0, 0 } },
13765		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13765	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13766	13766	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13767	13767	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13768	13768	0, 0 },

		@@ -13779,7 +13779,7 @@ const insn_template i386_optab[] =
13779	13779	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13780	13780	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13781	13781	0, 0, 0, 0, 0, 0 } },
13782		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13782	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13783	13783	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13784	13784	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13785	13785	0, 0 },

		@@ -13830,7 +13830,7 @@ const insn_template i386_optab[] =
13830	13830	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13831	13831	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13832	13832	0, 0, 0, 0, 0, 0 } },
13833		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13833	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13834	13834	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13835	13835	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13836	13836	0, 0 },

		@@ -13847,7 +13847,7 @@ const insn_template i386_optab[] =
13847	13847	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13848	13848	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13849	13849	0, 0, 0, 0, 0, 0 } },
13850		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13850	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13851	13851	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13852	13852	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13853	13853	0, 0 },

		@@ -13898,7 +13898,7 @@ const insn_template i386_optab[] =
13898	13898	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13899	13899	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13900	13900	0, 0, 0, 0, 0, 0 } },
13901		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13901	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13902	13902	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13903	13903	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13904	13904	0, 0 },

		@@ -13915,7 +13915,7 @@ const insn_template i386_optab[] =
13915	13915	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13916	13916	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13917	13917	0, 0, 0, 0, 0, 0 } },
13918		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13918	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13919	13919	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13920	13920	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13921	13921	0, 0 },

		@@ -13966,7 +13966,7 @@ const insn_template i386_optab[] =
13966	13966	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13967	13967	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13968	13968	0, 0, 0, 0, 0, 0 } },
13969		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13969	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13970	13970	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13971	13971	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13972	13972	0, 0 },

		@@ -13983,7 +13983,7 @@ const insn_template i386_optab[] =
13983	13983	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13984	13984	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13985	13985	0, 0, 0, 0, 0, 0 } },
13986		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	13986	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
13987	13987	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
13988	13988	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
13989	13989	0, 0 },

		@@ -14034,7 +14034,7 @@ const insn_template i386_optab[] =
14034	14034	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14035	14035	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14036	14036	0, 0, 0, 0, 0, 0 } },
14037		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14037	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14038	14038	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14039	14039	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14040	14040	0, 0 },

		@@ -14051,7 +14051,7 @@ const insn_template i386_optab[] =
14051	14051	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14052	14052	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14053	14053	0, 0, 0, 0, 0, 0 } },
14054		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14054	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14055	14055	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14056	14056	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14057	14057	0, 0 },

		@@ -14102,7 +14102,7 @@ const insn_template i386_optab[] =
14102	14102	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14103	14103	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14104	14104	0, 0, 0, 0, 0, 0 } },
14105		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14105	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14106	14106	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14107	14107	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14108	14108	0, 0 },

		@@ -14119,7 +14119,7 @@ const insn_template i386_optab[] =
14119	14119	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14120	14120	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14121	14121	0, 0, 0, 0, 0, 0 } },
14122		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14122	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14123	14123	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14124	14124	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14125	14125	0, 0 },

		@@ -14170,7 +14170,7 @@ const insn_template i386_optab[] =
14170	14170	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14171	14171	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14172	14172	0, 0, 0, 0, 0, 0 } },
14173		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14173	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14174	14174	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14175	14175	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14176	14176	0, 0 },

		@@ -14187,7 +14187,7 @@ const insn_template i386_optab[] =
14187	14187	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14188	14188	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14189	14189	0, 0, 0, 0, 0, 0 } },
14190		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14190	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14191	14191	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14192	14192	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14193	14193	0, 0 },

		@@ -14238,7 +14238,7 @@ const insn_template i386_optab[] =
14238	14238	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14239	14239	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14240	14240	0, 0, 0, 0, 0, 0 } },
14241		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14241	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14242	14242	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14243	14243	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14244	14244	0, 0 },

		@@ -14255,7 +14255,7 @@ const insn_template i386_optab[] =
14255	14255	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14256	14256	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14257	14257	0, 0, 0, 0, 0, 0 } },
14258		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14258	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14259	14259	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
14260	14260	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14261	14261	0, 0 },

		@@ -14306,7 +14306,7 @@ const insn_template i386_optab[] =
14306	14306	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14307	14307	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14308	14308	0, 0, 0, 0, 0, 0 } },
14309		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14309	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14310	14310	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14311	14311	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14312	14312	0, 0 },

		@@ -14326,7 +14326,7 @@ const insn_template i386_optab[] =
14326	14326	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14327	14327	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14328	14328	0, 0, 0, 0, 0, 0 } },
14329		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14329	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14330	14330	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14331	14331	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14332	14332	0, 0 },

		@@ -14607,7 +14607,7 @@ const insn_template i386_optab[] =
14607	14607	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14608	14608	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14609	14609	0, 0, 0, 0, 0, 0 } },
14610		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14610	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14611	14611	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14612	14612	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14613	14613	0, 0 },

		@@ -14624,7 +14624,7 @@ const insn_template i386_optab[] =
14624	14624	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14625	14625	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14626	14626	0, 0, 0, 0, 0, 0 } },
14627		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14627	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14628	14628	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14629	14629	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14630	14630	0, 0 },

		@@ -14703,7 +14703,7 @@ const insn_template i386_optab[] =
14703	14703	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14704	14704	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14705	14705	0, 0, 0, 0, 0, 0 } },
14706		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14706	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14707	14707	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14708	14708	0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14709	14709	0, 0 },

		@@ -14720,7 +14720,7 @@ const insn_template i386_optab[] =
14720	14720	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14721	14721	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14722	14722	0, 0, 0, 0, 0, 0 } },
14723		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14723	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14724	14724	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14725	14725	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14726	14726	0, 0 },

		@@ -14737,7 +14737,7 @@ const insn_template i386_optab[] =
14737	14737	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14738	14738	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14739	14739	0, 0, 0, 0, 0, 0 } },
14740		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14740	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14741	14741	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14742	14742	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14743	14743	0, 0 },

		@@ -14788,7 +14788,7 @@ const insn_template i386_optab[] =
14788	14788	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14789	14789	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14790	14790	0, 0, 0, 0, 0, 0 } },
14791		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14791	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14792	14792	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14793	14793	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14794	14794	0, 0 },

		@@ -14805,7 +14805,7 @@ const insn_template i386_optab[] =
14805	14805	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14806	14806	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14807	14807	0, 0, 0, 0, 0, 0 } },
14808		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14808	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14809	14809	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14810	14810	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14811	14811	0, 0 },

		@@ -14890,7 +14890,7 @@ const insn_template i386_optab[] =
14890	14890	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14891	14891	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14892	14892	0, 0, 0, 0, 0, 0 } },
14893		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14893	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14894	14894	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14895	14895	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14896	14896	0, 0 },

		@@ -14907,7 +14907,7 @@ const insn_template i386_optab[] =
14907	14907	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14908	14908	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14909	14909	0, 0, 0, 0, 0, 0 } },
14910		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14910	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14911	14911	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14912	14912	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14913	14913	0, 0 },

		@@ -14975,7 +14975,7 @@ const insn_template i386_optab[] =
14975	14975	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14976	14976	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14977	14977	0, 0, 0, 0, 0, 0 } },
14978		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14978	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14979	14979	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14980	14980	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14981	14981	0, 0 },

		@@ -14992,7 +14992,7 @@ const insn_template i386_optab[] =
14992	14992	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14993	14993	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14994	14994	0, 0, 0, 0, 0, 0 } },
14995		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	14995	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
14996	14996	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14997	14997	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
14998	14998	0, 0 },

		@@ -15060,7 +15060,7 @@ const insn_template i386_optab[] =
15060	15060	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15061	15061	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15062	15062	0, 0, 0, 0, 0, 0 } },
15063		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0,
	15063	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
15064	15064	1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
15065	15065	1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15066	15066	0, 0 },

		@@ -15077,7 +15077,7 @@ const insn_template i386_optab[] =
15077	15077	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15078	15078	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15079	15079	0, 0, 0, 0, 0, 0 } },
15080		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0,
	15080	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
15081	15081	1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
15082	15082	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15083	15083	0, 0 },

		@@ -15094,7 +15094,7 @@ const insn_template i386_optab[] =
15094	15094	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15095	15095	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15096	15096	0, 0, 0, 0, 0, 0 } },
15097		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	15097	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
15098	15098	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15099	15099	1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15100	15100	0, 0 },

		@@ -15111,7 +15111,7 @@ const insn_template i386_optab[] =
15111	15111	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15112	15112	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15113	15113	0, 0, 0, 0, 0, 0 } },
15114		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	15114	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
15115	15115	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15116	15116	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15117	15117	0, 0 },

		@@ -15264,7 +15264,7 @@ const insn_template i386_optab[] =
15264	15264	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15265	15265	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15266	15266	0, 0, 0, 0, 0, 0 } },
15267		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	15267	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
15268	15268	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15269	15269	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15270	15270	0, 0 },

		@@ -15281,7 +15281,7 @@ const insn_template i386_optab[] =
15281	15281	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15282	15282	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15283	15283	0, 0, 0, 0, 0, 0 } },
15284		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	15284	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
15285	15285	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15286	15286	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15287	15287	0, 0 },

		@@ -15332,7 +15332,7 @@ const insn_template i386_optab[] =
15332	15332	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15333	15333	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15334	15334	0, 0, 0, 0, 0, 0 } },
15335		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	15335	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
15336	15336	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15337	15337	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15338	15338	0, 0 },

		@@ -15349,7 +15349,7 @@ const insn_template i386_optab[] =
15349	15349	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15350	15350	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15351	15351	0, 0, 0, 0, 0, 0 } },
15352		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	15352	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
15353	15353	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15354	15354	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
15355	15355	0, 0 },

		@@ -16161,7 +16161,7 @@ const insn_template i386_optab[] =
16161	16161	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16162	16162	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16163	16163	0, 0, 0, 0, 0, 0 } },
16164		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16164	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16165	16165	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16166	16166	1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16167	16167	0, 0 },

		@@ -16178,7 +16178,7 @@ const insn_template i386_optab[] =
16178	16178	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16179	16179	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16180	16180	0, 0, 0, 0, 0, 0 } },
16181		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16181	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16182	16182	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16183	16183	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16184	16184	0, 0 },

		@@ -16229,7 +16229,7 @@ const insn_template i386_optab[] =
16229	16229	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16230	16230	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16231	16231	0, 0, 0, 0, 0, 0 } },
16232		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16232	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16233	16233	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16234	16234	1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16235	16235	0, 0 },

		@@ -16246,7 +16246,7 @@ const insn_template i386_optab[] =
16246	16246	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16247	16247	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16248	16248	0, 0, 0, 0, 0, 0 } },
16249		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16249	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16250	16250	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16251	16251	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16252	16252	0, 0 },

		@@ -16311,7 +16311,7 @@ const insn_template i386_optab[] =
16311	16311	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16312	16312	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16313	16313	0, 0, 0, 0, 0, 0 } },
16314		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16314	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16315	16315	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16316	16316	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16317	16317	0, 0 },

		@@ -16331,7 +16331,7 @@ const insn_template i386_optab[] =
16331	16331	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16332	16332	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16333	16333	0, 0, 0, 0, 0, 0 } },
16334		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16334	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16335	16335	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16336	16336	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16337	16337	0, 0 },

		@@ -16351,7 +16351,7 @@ const insn_template i386_optab[] =
16351	16351	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16352	16352	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16353	16353	0, 0, 0, 0, 0, 0 } },
16354		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16354	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16355	16355	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16356	16356	1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16357	16357	0, 0 },

		@@ -16368,7 +16368,7 @@ const insn_template i386_optab[] =
16368	16368	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16369	16369	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16370	16370	0, 0, 0, 0, 0, 0 } },
16371		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16371	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16372	16372	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16373	16373	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16374	16374	0, 0 },

		@@ -16447,7 +16447,7 @@ const insn_template i386_optab[] =
16447	16447	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16448	16448	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16449	16449	0, 0, 0, 0, 0, 0 } },
16450		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16450	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16451	16451	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16452	16452	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16453	16453	0, 0 },

		@@ -16464,7 +16464,7 @@ const insn_template i386_optab[] =
16464	16464	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16465	16465	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16466	16466	0, 0, 0, 0, 0, 0 } },
16467		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16467	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16468	16468	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16469	16469	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16470	16470	0, 0 },

		@@ -16549,7 +16549,7 @@ const insn_template i386_optab[] =
16549	16549	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16550	16550	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16551	16551	0, 0, 0, 0, 0, 0 } },
16552		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16552	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16553	16553	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16554	16554	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16555	16555	0, 0 },

		@@ -16566,7 +16566,7 @@ const insn_template i386_optab[] =
16566	16566	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16567	16567	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16568	16568	0, 0, 0, 0, 0, 0 } },
16569		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16569	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16570	16570	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16571	16571	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16572	16572	0, 0 },

		@@ -16583,7 +16583,7 @@ const insn_template i386_optab[] =
16583	16583	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16584	16584	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16585	16585	0, 0, 0, 0, 0, 0 } },
16586		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16586	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16587	16587	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16588	16588	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16589	16589	0, 0 },

		@@ -16600,7 +16600,7 @@ const insn_template i386_optab[] =
16600	16600	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16601	16601	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16602	16602	0, 0, 0, 0, 0, 0 } },
16603		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16603	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16604	16604	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16605	16605	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16606	16606	0, 0 },

		@@ -16617,7 +16617,7 @@ const insn_template i386_optab[] =
16617	16617	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16618	16618	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16619	16619	0, 0, 0, 0, 0, 0 } },
16620		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16620	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16621	16621	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16622	16622	1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16623	16623	0, 0 },

		@@ -16634,7 +16634,7 @@ const insn_template i386_optab[] =
16634	16634	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16635	16635	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16636	16636	0, 0, 0, 0, 0, 0 } },
16637		- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
	16637	+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
16638	16638	1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16639	16639	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
16640	16640	0, 0 },

binutils_os216 Fork