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d: Fix ICE in uda_attribute_p when looking up unknown attribute

The target attribute table is not guaranteed to be set in all backends.

gcc/d/ChangeLog:

PR d/95173
* d-attribs.cc (uda_attribute_p): Don't search target attribute table
if NULL.

gcc/testsuite/ChangeLog:

PR d/95173
* gdc.dg/pr95173.d: New test.

d: Don't set DECL_INITIAL if initializer is 'void'.

Declarations initialized with `= void` were being default initialized.
That is not really the intent, and misses the small optimization that
should have been gained from using void initializations.

gcc/d/ChangeLog:

* decl.cc (DeclVisitor::visit (VarDeclaration *)): Don't set
DECL_INITIAL if initializer is 'void'.

gcc/testsuite/ChangeLog:

* gdc.dg/init1.d: New test.

d: Turn on deprecation warnings by default.

This is the default in the upstream reference compiler, and can reduce
some confusion when comparing warning/error messages of gdc and dmd side
by side.

Merges libphobos with upstream druntime d05ebaad and phobos 021ae0df7.

Reviewed-on: https://github.com/dlang/druntime/pull/3127
https://github.com/dlang/phobos/pull/7521

gcc/d/ChangeLog:

* d-lang.cc (d_init_options): Turn on deprecation warnings by default.

libphobos/ChangeLog:

* libdruntime/MERGE: Merge upstream druntime d05ebaad.
* src/MERGE: Merge upstream phobos 021ae0df7.
* testsuite/libphobos.typeinfo/struct-align.d: Remove empty statement.

gcc/testsuite/ChangeLog:

* gdc.dg/asm1.d: Don't use deprecated asm syntax.
* gdc.dg/compilable.d: Add public to selective import.
* gdc.dg/lto/ltotests_0.d: Explicitly catch Throwable.
* gdc.dg/runnable.d: Remove empty statement.

d: Merge upstream dmd 4f1046222.

Renames OnScopeStatement to ScopeGuardStatement.

Reviewed-on: https://github.com/dlang/dmd/pull/11285

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd 4f1046222.
* toir.cc (IRVisitor::visit (OnScopeGuardStatement *)): Rename to ...
(IRVisitor::visit (ScopeGuardStatement *)): ... this.

Fortran: Fix character-kind=4 substring resolution (PR95837)

Testing showed that it is always set and its value matches
always ts->kind (if available) or otherwise, if it is a variable,
the sym->ts.kind.

gcc/fortran/ChangeLog:

PR fortran/95837
* resolve.c (gfc_resolve_substring_charlen): Remove
bogus ts.kind setting for the expression.

gcc/testsuite/ChangeLog:

PR fortran/95837
* gfortran.dg/char4-subscript.f90: New test.

Merge master 92bed036098

c++: Improve access checking inside templates [PR41437]

Merge master a97e49a89d1

tree-optimization/95839 - allow CTOR vectorization without loads

This removes a premature check for enough datarefs in a basic-block
before we consider vectorizing it which leaves basic-blocks with
just vectorizable vector constructors unvectorized. The check
is effectively done by the following check for store groups
which then also include constructors.

2020-06-25 Richard Biener <rguenther@suse.de>

PR tree-optimization/95839
* tree-vect-slp.c (vect_slp_analyze_bb_1): Remove premature
check on the number of datarefs.

* gcc.dg/vect/bb-slp-pr95839.c: New testcase.

coroutines: Add a cleanup expression for g-r-o when needed [PR95477].

The PR reports that we fail to destroy the object initially created from
the get-return-object call. Fixed by adding a cleanup when the DTOR is
non-trivial. In addition, to meet the specific wording that the call to
get_return_object creates the glvalue for the return, we must construct
that in-place in the return object to avoid a second copy/move CTOR.

gcc/cp/ChangeLog:

PR c++/95477
* coroutines.cc (morph_fn_to_coro): Apply a cleanup to
the get return object when the DTOR is non-trivial.

gcc/testsuite/ChangeLog:

PR c++/95477
* g++.dg/coroutines/pr95477.C: New test.
* g++.dg/coroutines/void-gro-non-class-coro.C: New test.

(cherry picked from commit 788b962aa00959e861b45767c5c88ec41ca30c21)

powerpc: Restore bootstrap for Darwin.

Darwin has signed chars and the fields in the insn_data
struct are const char, which leads to the fail.

gcc/ChangeLog:

* config/rs6000/rs6000-call.c (mma_init_builtins): Cast
the insn_data n_operands value to unsigned.

fortran: Fix ICE when 'if' clause used with 'target parallel' (PR95869)

2020-06-25 Tobias Burnus <tobias@codesourcery.com>
Kwok Cheung Yeung <kcy@codesourery.com>

gcc/fortran/

PR fortran/95869
* trans-openmp.c (gfc_trans_omp_target): Use correct scoping block.

gcc/testsuite/

PR fortran/95869
* gfortran.dg/gomp/combined-if.f90 (test_target_parallel): Re-enable.
* gfortran.dg/gomp/pr95869.f90: New.

fortran: Apply if clause to all sub-constructs in combined OpenMP constructs

The unmodified 'if' clause should be applied to all the sub-constructs that
accept an 'if' clause in a combined OpenMP construct, and not just to the
'parallel' sub-construct.

2020-06-25 Kwok Cheung Yeung <kcy@codesourcery.com>

gcc/fortran/

* trans-openmp.c (gfc_split_omp_clauses): Add if clause
to target and simd sub-constructs.

gcc/testsuite/

* gfortran.dg/gomp/combined-if.f90: New.

Reviewed-by: Jakub Jelinek <jakub@redhat.com>

Always use SLP vector defs to determine insertion place

With the last vectorizable_shift patch we can now always use the
SLP vector defs to determine the vectorized stmt insertion place,
paving the way for a "verifier" for pending restructuring and
BB vectorization of reductions and other live stmts.

2020-06-25 Richard Biener <rguenther@suse.de>

* tree-vect-slp.c (vect_schedule_slp_instance): Always use
vector defs to determine insertion place.

x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENT

CLWB isn't supported on Ice Lake client. But Ice Lake server support it.
Move PTA_CLWB to PTA_ICELAKE_SERVER.

PR target/95874
* config/i386/i386.c (PTA_ICELAKE_CLIENT): Remove PTA_CLWB.
(PTA_ICELAKE_SERVER): Add PTA_CLWB.

(cherry picked from commit c422e5f81f42a0fc197f0715f4fcd81f1be90bff)

x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENT

CLWB isn't supported on Ice Lake client. But Ice Lake server support it.
Move PTA_CLWB to PTA_ICELAKE_SERVER.

PR target/95874
* config/i386/i386.h (PTA_ICELAKE_CLIENT): Remove PTA_CLWB.
(PTA_ICELAKE_SERVER): Add PTA_CLWB.

(cherry picked from commit c422e5f81f42a0fc197f0715f4fcd81f1be90bff)

x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENT

CLWB isn't supported on Ice Lake client. But Ice Lake server and Tiger
Lake support it. Move PTA_CLWB to PTA_ICELAKE_SERVER and PTA_TIGERLAKE.

PR target/95874
* config/i386/i386.h (PTA_ICELAKE_CLIENT): Remove PTA_CLWB.
(PTA_ICELAKE_SERVER): Add PTA_CLWB.
(PTA_TIGERLAKE): Add PTA_CLWB.

(cherry picked from commit c422e5f81f42a0fc197f0715f4fcd81f1be90bff)

x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENT

CLWB isn't supported on Ice Lake client. But Ice Lake server and Tiger
Lake support it. Move PTA_CLWB to PTA_ICELAKE_SERVER and PTA_TIGERLAKE.

PR target/95874
* config/i386/i386.h (PTA_ICELAKE_CLIENT): Remove PTA_CLWB.
(PTA_ICELAKE_SERVER): Add PTA_CLWB.
(PTA_TIGERLAKE): Add PTA_CLWB.

tree-optimization/95866 - avoid using scalar ops for vectorized shift

This avoids using the original scalar SSA operand when vectorizing
a shift with a vectorized shift operand where we know all vector
components have the same value and thus we can use a vector by
scalar shift. Using the scalar SSA operand causes a possibly
long chain of scalar computation to be retained so it's better
to simply extract lane zero from the available vectorized shift
operand.

2020-06-25 Richard Biener <rguenther@suse.de>

PR tree-optimization/95866
* tree-vect-stmts.c (vectorizable_shift): Reject incompatible
vectorized shift operands. For scalar shifts use lane zero
of a vectorized shift operand.

* gcc.dg/vect/bb-slp-pr95866.c: New testcase.

gcov-tool: fix merge operation for summary

libgcc/ChangeLog:

* libgcov-driver.c (merge_summary): Remove function as its name
is misleading and doing something different.
(dump_one_gcov): Add ATTRIBUTE_UNUSED for 2 args. Take read summary
in gcov-tool.
* libgcov-util.c (curr_object_summary): Remove.
(read_gcda_file): Remove unused curr_object_summary.
(gcov_merge): Merge summaries.
* libgcov.h: Add summary argument for gcov_info struct.

VEC_COND_EXPR: clean up first argument

gcc/ChangeLog:

PR tree-optimization/95745
PR middle-end/95830
* gimple-isel.cc (gimple_expand_vec_cond_exprs): Delete dead
SSA_NAMEs used as the first argument of a VEC_COND_EXPR. Always
return 0.
* tree-vect-generic.c (expand_vector_condition): Remove dead
SSA_NAMEs used as the first argument of a VEC_COND_EXPR.

Daily bump.

Daily bump.

Daily bump.

Daily bump.

rs6000: Add MMA built-in function definitions and test cases

Add the Matrix-Multiply Assist (MMA) built-ins. The MMA accumulators are
INOUT operands for most MMA instructions, but they are also very expensive
to move around. For this reason, we have implemented a built-in API where
the accumulators are passed using pass-by-reference/pointers, so the user
won't use one accumulator as input and another as output, which wouldentail
a lot of copies. However, using pointers gives us poor code generation
when we expand the built-ins at normal expand time. We therefore expand
the MMA built-ins early into gimple, converting the pass-by-reference calls
to an internal built-in that uses pass-by-value calling convention, where
we can enforce the input and output accumulators are the same. This gives
us much better code generation.

2020-06-20 Peter Bergner <bergner@linux.ibm.com>

gcc/
* config/rs6000/predicates.md (mma_assemble_input_operand): New.
* config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3,
BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA
built-in functions.
(ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR,
PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN,
PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP,
PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN,
PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN,
PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP,
PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4,
PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP,
XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2,
XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER,
XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN,
XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S,
XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP,
XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins.
* config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P.
Allow zero constants.
(print_operand) <case 'A'>: New output modifier.
(rs6000_split_multireg_move): Add support for inserting accumulator
priming and depriming instructions. Add support for splitting an
assemble accumulator pattern.
* config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin,
rs6000_gimple_fold_mma_builtin): New functions.
(RS6000_BUILTIN_M): New macro.
(def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes.
(bdesc_mma): Add new MMA built-in support.
(htm_expand_builtin): Use RS6000_BTC_OPND_MASK.
(rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and
RS6000_BTM_MMA.
(rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute.
(rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p
and rs6000_gimple_fold_mma_builtin.
(rs6000_expand_builtin): Call mma_expand_builtin.
Use RS6000_BTC_OPND_MASK.
(rs6000_init_builtins): Adjust comment. Call mma_init_builtins.
(htm_init_builtins): Use RS6000_BTC_OPND_MASK.
(builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and
VSX_BUILTIN_XVCVBF16SP.
* config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY,
RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR,
RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines.
(RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST,
RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values.
* config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant.
(UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2,
UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP,
UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP,
UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN,
UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN,
UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER,
UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP,
UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP,
UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN,
UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN,
UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2,
UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S,
UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8,
UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4,
UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP,
UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN,
UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN,
UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN,
UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP,
UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP,
UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER,
UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN,
UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP,
UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8,
UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP,
UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New.
(MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8,
MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4,
MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4,
MMA_AVVI4I4I4): New define_int_iterator.
(acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2,
avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4,
avvi4i4i4): New define_int_attr.
(*movpxi): Add zero constant alternative.
(mma_assemble_pair, mma_assemble_acc): New define_expand.
(*mma_assemble_acc): New define_insn_and_split.
(mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>,
mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>,
mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>,
mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn.
* config/rs6000/rs6000.md (define_attr "type"): New type mma.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New.
(UNSPEC_VSX_XVCVSPBF16): Likewise.
(XVCVBF16): New define_int_iterator.
(xvcvbf16): New define_int_attr.
(vsx_<xvcvbf16>): New define_insn.
* doc/extend.texi: Document the mma built-ins.

gcc/testsuite/
* gcc.target/powerpc/mma-builtin-1.c: New test.
* gcc.target/powerpc/mma-builtin-2.c: New test.
* gcc.target/powerpc/mma-builtin-3.c: New test.
* gcc.target/powerpc/mma-builtin-4.c: New test.
* gcc.target/powerpc/mma-builtin-5.c: New test.
* gcc.target/powerpc/mma-builtin-6.c: New test.

(cherry picked from commit 8ee2640bfdc62f835ec9740278f948034bc7d9f1)

rs6000: Backport u8bit_cint_operand predicate

Backport from master.

2020-05-11 Kelvin Nilsen <wschmidt@linux.ibm.com>

gcc/
* config/rs6000/predicates.md (u8bit_cint_operand): New predicate.

rs6000: Add base support and types for defining MMA built-ins

Add the new -mmma option as well as the initial MMA support, which includes
the target specific __vector_pair and __vector_quad types, the POImode and
PXImode partial integer modes they are mapped to, and their associated
move patterns. Support for the restrictions on the registers these modes
can be assigned to as also been added.

2020-06-20 Peter Bergner <bergner@linux.ibm.com>
Michael Meissner <meissner@linux.ibm.com>

gcc/
* config/rs6000/mma.md: New file.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__MMA__ for mma.
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support
for __vector_pair and __vector_quad types.
* config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add
OPTION_MASK_MMA.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000-modes.def (OI, XI): New integer modes.
(POI, PXI): New partial integer modes.
* config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define.
(rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
Add support for POImode being allowed in VSX registers and PXImode
being allowed in FP registers.
(rs6000_modes_tieable_p): Adjust comment.
Add support for POImode and PXImode.
(rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode
XImode, PXImode, V2SImode, V2SFmode and CCFPmode..
(rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P.
Set up appropriate addr_masks for vector pair and vector quad addresses.
(rs6000_init_hard_regno_mode_ok): Add support for vector pair and
vector quad registers. Setup reload handlers for POImode and PXImode.
(rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA.
(rs6000_option_override_internal): Error if -mmma is specified
without -mcpu=future.
(rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P.
(quad_address_p): Change size test to less than 16 bytes.
(reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair
and vector quad instructions.
(avoiding_indexed_address_p): Likewise.
(rs6000_emit_move): Disallow POImode and PXImode moves involving
constants.
(rs6000_preferred_reload_class): Prefer VSX registers for POImode
and FP registers for PXImode.
(rs6000_split_multireg_move): Support splitting POImode and PXImode
move instructions.
(rs6000_mangle_type): Adjust comment. Add support for mangling
__vector_pair and __vector_quad types.
(rs6000_opt_masks): Add entry for mma.
(rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_function_value): Use VECTOR_ALIGNMENT_P.
(address_to_insn_form): Likewise.
(reg_to_non_prefixed): Likewise.
(rs6000_invalid_conversion): New function.
* config/rs6000/rs6000.h (MASK_MMA): Define.
(BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled.
(VECTOR_ALIGNMENT_P): New helper macro.
(ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P.
(RS6000_BTM_MMA): Define.
(RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and
RS6000_BTI_vector_quad.
(vector_pair_type_node): New.
(vector_quad_type_node): New.
* config/rs6000/rs6000.md: Include mma.md.
(define_mode_iterator RELOAD): Add POI and PXI.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md.
* config/rs6000/rs6000.opt (-mmma): New.
* doc/invoke.texi: Document -mmma.

(cherry picked from commit f002c046e37d0027513af5297d9259e1fad29c27)

Merge small partitions.

Current partitioner seems to create one huge partitions and several
other small partitions. This commit improves the partitioning
algorithm by merging small partitions together. It also avoids wasting
time partitioning if the program size is `small'. Note that small here
is subjective.

gcc/ChangeLog:
2020-06-24 Giuliano Belinassi <giuliano.belinassi@usp.br>

* cgraphunit.c (ipa_passes): Assert for non-empty partition.
* lto-partition.c: Remove currrent_working_partition.
(add_symbol_to_partition): Remove useless check.
(lto_max_no_alonevap_map): Use an heuristic to merge small
partitions. Also fix creation of empty partitions.

[PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtin

Hi,
Fix codegen for builtin vec_pack_to_short_fp32. This includes adding
a define_insn for xvcvsphp, and adding a new define_expand for
convert_4f32_8f16.

2020-06-24 Will Schmidt <will_schmidt@vnet.ibm.com>

PR target/94954

gcc
* config/rs6000/altivec.h (vec_pack_to_short_fp32): Update.
* config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec.
(convert_4f32_8f16): New define_expand
* config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define
and overload.
* config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New
overloaded builtin entry.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec.
(vsx_xvcvsphp): New define_insn.

gcc/testsuite
* gcc.target/powerpc/builtins-1-p9-runnable.c: Update.

Revert "PR fortran/95689 - ICE in check_sym_interfaces, at fortran/interface.c:2015"

With submodules, name mangling of interfaces may result in long internal
symbols overflowing an internal buffer. We now check that we do not
exceed the enlarged buffer size.

gcc/fortran/
PR fortran/95689
* interface.c (check_sym_interfaces): Enlarge temporary buffer,
and add check on length on mangled name to prevent overflow.

gcc/testsuite/
PR fortran/95689
* gfortran.dg/pr95689.f90: New test.

(reverts the cherry-pick from commit 62c0c0ea7bfb6f8f6b8d767b05120cafb6823da6)