hardware/intel/intel-driver
Revisión | 1bf4e4822373cb7e5d5a559571cc4bd1ef3c1fb3 (tree) |
---|---|
Tiempo | 2014-12-14 01:26:32 |
Autor | Zhao Yakui <yakui.zhao@inte...> |
Commiter | Xiang, Haihao |
Skl: Add the PCIIDs and initial driver-codec info for Skl
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 7d3be309fed0330097426ffd5a055cb2db473236)
Conflicts:
src/intel_driver.h
@@ -306,6 +306,49 @@ static struct hw_codec_info chv_hw_codec_info = { | ||
306 | 306 | }, |
307 | 307 | }; |
308 | 308 | |
309 | +/* TODO: Add the separate call back function for Gen9 */ | |
310 | +static struct hw_codec_info skl_hw_codec_info = { | |
311 | + .dec_hw_context_init = gen8_dec_hw_context_init, | |
312 | + .enc_hw_context_init = gen8_enc_hw_context_init, | |
313 | + .proc_hw_context_init = gen75_proc_context_init, | |
314 | + .render_init = gen8_render_init, | |
315 | + .post_processing_context_init = gen8_post_processing_context_init, | |
316 | + | |
317 | + .max_width = 4096, | |
318 | + .max_height = 4096, | |
319 | + .min_linear_wpitch = 64, | |
320 | + .min_linear_hpitch = 16, | |
321 | + | |
322 | + .h264_mvc_dec_profiles = (VA_PROFILE_MASK(H264StereoHigh) | | |
323 | + VA_PROFILE_MASK(H264MultiviewHigh)), | |
324 | + .h264_dec_chroma_formats = EXTRA_H264_DEC_CHROMA_FORMATS, | |
325 | + .jpeg_dec_chroma_formats = EXTRA_JPEG_DEC_CHROMA_FORMATS, | |
326 | + | |
327 | + .has_mpeg2_decoding = 1, | |
328 | + .has_mpeg2_encoding = 1, | |
329 | + .has_h264_decoding = 1, | |
330 | + .has_h264_encoding = 1, | |
331 | + .has_vc1_decoding = 1, | |
332 | + .has_jpeg_decoding = 1, | |
333 | + .has_vpp = 1, | |
334 | + .has_accelerated_getimage = 1, | |
335 | + .has_accelerated_putimage = 1, | |
336 | + .has_tiled_surface = 1, | |
337 | + .has_di_motion_adptive = 1, | |
338 | + .has_di_motion_compensated = 1, | |
339 | + .has_vp8_decoding = 1, | |
340 | + .has_h264_mvc_encoding = 1, | |
341 | + | |
342 | + .num_filters = 5, | |
343 | + .filters = { | |
344 | + { VAProcFilterNoiseReduction, I965_RING_VEBOX }, | |
345 | + { VAProcFilterDeinterlacing, I965_RING_VEBOX }, | |
346 | + { VAProcFilterSharpening, I965_RING_NULL }, /* need to rebuild the shader for BDW */ | |
347 | + { VAProcFilterColorBalance, I965_RING_VEBOX}, | |
348 | + { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX}, | |
349 | + }, | |
350 | +}; | |
351 | + | |
309 | 352 | struct hw_codec_info * |
310 | 353 | i965_get_codec_info(int devid) |
311 | 354 | { |
@@ -427,6 +470,13 @@ static const struct intel_device_info chv_device_info = { | ||
427 | 470 | .is_cherryview = 1, |
428 | 471 | }; |
429 | 472 | |
473 | +static const struct intel_device_info skl_device_info = { | |
474 | + .gen = 9, | |
475 | + | |
476 | + .urb_size = 4096, | |
477 | + .max_wm_threads = 64, /* per PSD */ | |
478 | +}; | |
479 | + | |
430 | 480 | const struct intel_device_info * |
431 | 481 | i965_get_device_info(int devid) |
432 | 482 | { |
@@ -133,3 +133,18 @@ CHIPSET(0x22B0, chv, chv, "Intel(R) CherryView") | ||
133 | 133 | CHIPSET(0x22B1, chv, chv, "Intel(R) CherryView") |
134 | 134 | CHIPSET(0x22B2, chv, chv, "Intel(R) CherryView") |
135 | 135 | CHIPSET(0x22B3, chv, chv, "Intel(R) CherryView") |
136 | +CHIPSET(0x1902, skl, skl, "Intel(R) Skylake") | |
137 | +CHIPSET(0x1906, skl, skl, "Intel(R) Skylake") | |
138 | +CHIPSET(0x190E, skl, skl, "Intel(R) Skylake") | |
139 | +CHIPSET(0x1912, skl, skl, "Intel(R) Skylake") | |
140 | +CHIPSET(0x1913, skl, skl, "Intel(R) Skylake") | |
141 | +CHIPSET(0x1915, skl, skl, "Intel(R) Skylake") | |
142 | +CHIPSET(0x1916, skl, skl, "Intel(R) Skylake") | |
143 | +CHIPSET(0x1917, skl, skl, "Intel(R) Skylake") | |
144 | +CHIPSET(0x191B, skl, skl, "Intel(R) Skylake") | |
145 | +CHIPSET(0x191E, skl, skl, "Intel(R) Skylake") | |
146 | +CHIPSET(0x1921, skl, skl, "Intel(R) Skylake") | |
147 | +CHIPSET(0x1926, skl, skl, "Intel(R) Skylake") | |
148 | +CHIPSET(0x192B, skl, skl, "Intel(R) Skylake") | |
149 | +CHIPSET(0x193A, skl, skl, "Intel(R) Skylake") | |
150 | +CHIPSET(0x193B, skl, skl, "Intel(R) Skylake") |
@@ -192,4 +192,6 @@ struct intel_region | ||
192 | 192 | #define IS_CHERRYVIEW(device_info) (device_info->is_cherryview) |
193 | 193 | #define IS_GEN8(device_info) (device_info->gen == 8) |
194 | 194 | |
195 | +#define IS_GEN9(device_info) (device_info->gen == 9) | |
196 | + | |
195 | 197 | #endif /* _INTEL_DRIVER_H_ */ |