hardware/intel/intel-driver
Revisión | 73e2bbccb3d127f2ccb34380773029689b449633 (tree) |
---|---|
Tiempo | 2016-05-27 14:24:29 |
Autor | Zhao Yakui <yakui.zhao@inte...> |
Commiter | Xiang, Haihao |
Add some utility functions for i965_gpe_resources
This is to add the wrapper function required by vp9 encoding.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Sean V Kelley <sean.v.kelley@intel.com>
@@ -787,6 +787,7 @@ const int vdenc_hme_cost[8][52] = { | ||
787 | 787 | buffer.tiling = I915_TILING_NONE; \ |
788 | 788 | i965_allocate_gpe_resource(i965->intel.bufmgr, \ |
789 | 789 | &buffer, \ |
790 | + bfsize, \ | |
790 | 791 | (des)); \ |
791 | 792 | } while (0) |
792 | 793 |
@@ -635,6 +635,8 @@ | ||
635 | 635 | #define I965_SURFACEFORMAT_R16G16B16_SSCALED 0x19E |
636 | 636 | #define I965_SURFACEFORMAT_R16G16B16_USCALED 0x19F |
637 | 637 | |
638 | +#define I965_SURFACEFORMAT_RAW 0x1FF | |
639 | + | |
638 | 640 | #define I965_CULLMODE_BOTH 0 |
639 | 641 | #define I965_CULLMODE_NONE 1 |
640 | 642 | #define I965_CULLMODE_FRONT 2 |
@@ -1323,8 +1323,13 @@ gen9_gpe_pipeline_end(VADriverContextP ctx, | ||
1323 | 1323 | Bool |
1324 | 1324 | i965_allocate_gpe_resource(dri_bufmgr *bufmgr, |
1325 | 1325 | struct i965_gpe_resource *res, |
1326 | + int size, | |
1326 | 1327 | const char *name) |
1327 | 1328 | { |
1329 | + if (!res || !size) | |
1330 | + return false; | |
1331 | + | |
1332 | + res->size = size; | |
1328 | 1333 | res->bo = dri_bo_alloc(bufmgr, name, res->size, 4096); |
1329 | 1334 | res->map = NULL; |
1330 | 1335 |
@@ -1602,3 +1607,451 @@ gen8_gpe_context_set_dynamic_buffer(VADriverContextP ctx, | ||
1602 | 1607 | |
1603 | 1608 | return; |
1604 | 1609 | } |
1610 | + | |
1611 | +void * | |
1612 | +gen8p_gpe_context_map_curbe(struct i965_gpe_context *gpe_context) | |
1613 | +{ | |
1614 | + dri_bo_map(gpe_context->dynamic_state.bo, 1); | |
1615 | + | |
1616 | + return (char *)gpe_context->dynamic_state.bo->virtual + gpe_context->curbe_offset; | |
1617 | +} | |
1618 | + | |
1619 | +void | |
1620 | +gen8p_gpe_context_unmap_curbe(struct i965_gpe_context *gpe_context) | |
1621 | +{ | |
1622 | + dri_bo_unmap(gpe_context->dynamic_state.bo); | |
1623 | +} | |
1624 | + | |
1625 | +void | |
1626 | +gen9_gpe_reset_binding_table(VADriverContextP ctx, | |
1627 | + struct i965_gpe_context *gpe_context) | |
1628 | +{ | |
1629 | + unsigned int *binding_table; | |
1630 | + unsigned int binding_table_offset = gpe_context->surface_state_binding_table.binding_table_offset; | |
1631 | + int i; | |
1632 | + | |
1633 | + dri_bo_map(gpe_context->surface_state_binding_table.bo, 1); | |
1634 | + binding_table = (unsigned int*)((char *)gpe_context->surface_state_binding_table.bo->virtual + binding_table_offset); | |
1635 | + | |
1636 | + for (i = 0; i < gpe_context->surface_state_binding_table.max_entries; i++) { | |
1637 | + *(binding_table + i) = gpe_context->surface_state_binding_table.surface_state_offset + i * SURFACE_STATE_PADDED_SIZE_GEN9; | |
1638 | + } | |
1639 | + | |
1640 | + dri_bo_unmap(gpe_context->surface_state_binding_table.bo); | |
1641 | +} | |
1642 | + | |
1643 | +void | |
1644 | +gen8_gpe_setup_interface_data(VADriverContextP ctx, | |
1645 | + struct i965_gpe_context *gpe_context) | |
1646 | +{ | |
1647 | + struct gen8_interface_descriptor_data *desc; | |
1648 | + int i; | |
1649 | + dri_bo *bo; | |
1650 | + unsigned char *desc_ptr; | |
1651 | + | |
1652 | + bo = gpe_context->dynamic_state.bo; | |
1653 | + dri_bo_map(bo, 1); | |
1654 | + assert(bo->virtual); | |
1655 | + desc_ptr = (unsigned char *)bo->virtual + gpe_context->idrt_offset; | |
1656 | + desc = (struct gen8_interface_descriptor_data *)desc_ptr; | |
1657 | + | |
1658 | + for (i = 0; i < gpe_context->num_kernels; i++) { | |
1659 | + struct i965_kernel *kernel; | |
1660 | + | |
1661 | + kernel = &gpe_context->kernels[i]; | |
1662 | + assert(sizeof(*desc) == 32); | |
1663 | + | |
1664 | + /*Setup the descritor table*/ | |
1665 | + memset(desc, 0, sizeof(*desc)); | |
1666 | + desc->desc0.kernel_start_pointer = kernel->kernel_offset >> 6; | |
1667 | + desc->desc3.sampler_count = 0; | |
1668 | + desc->desc3.sampler_state_pointer = gpe_context->sampler_offset; | |
1669 | + desc->desc4.binding_table_entry_count = 0; | |
1670 | + desc->desc4.binding_table_pointer = (gpe_context->surface_state_binding_table.binding_table_offset >> 5); | |
1671 | + desc->desc5.constant_urb_entry_read_offset = 0; | |
1672 | + desc->desc5.constant_urb_entry_read_length = ALIGN(gpe_context->curbe.length, 32) >> 5; // in registers | |
1673 | + | |
1674 | + desc++; | |
1675 | + } | |
1676 | + | |
1677 | + dri_bo_unmap(bo); | |
1678 | +} | |
1679 | + | |
1680 | +static void | |
1681 | +gen9_gpe_set_surface_tiling(struct gen9_surface_state *ss, unsigned int tiling) | |
1682 | +{ | |
1683 | + switch (tiling) { | |
1684 | + case I915_TILING_NONE: | |
1685 | + ss->ss0.tiled_surface = 0; | |
1686 | + ss->ss0.tile_walk = 0; | |
1687 | + break; | |
1688 | + case I915_TILING_X: | |
1689 | + ss->ss0.tiled_surface = 1; | |
1690 | + ss->ss0.tile_walk = I965_TILEWALK_XMAJOR; | |
1691 | + break; | |
1692 | + case I915_TILING_Y: | |
1693 | + ss->ss0.tiled_surface = 1; | |
1694 | + ss->ss0.tile_walk = I965_TILEWALK_YMAJOR; | |
1695 | + break; | |
1696 | + } | |
1697 | +} | |
1698 | + | |
1699 | +static void | |
1700 | +gen9_gpe_set_surface2_tiling(struct gen9_surface_state2 *ss, unsigned int tiling) | |
1701 | +{ | |
1702 | + switch (tiling) { | |
1703 | + case I915_TILING_NONE: | |
1704 | + ss->ss2.tiled_surface = 0; | |
1705 | + ss->ss2.tile_walk = 0; | |
1706 | + break; | |
1707 | + case I915_TILING_X: | |
1708 | + ss->ss2.tiled_surface = 1; | |
1709 | + ss->ss2.tile_walk = I965_TILEWALK_XMAJOR; | |
1710 | + break; | |
1711 | + case I915_TILING_Y: | |
1712 | + ss->ss2.tiled_surface = 1; | |
1713 | + ss->ss2.tile_walk = I965_TILEWALK_YMAJOR; | |
1714 | + break; | |
1715 | + } | |
1716 | +} | |
1717 | + | |
1718 | +static void | |
1719 | +gen9_gpe_set_2d_surface_state(struct gen9_surface_state *ss, | |
1720 | + unsigned int cacheability_control, | |
1721 | + unsigned int format, | |
1722 | + unsigned int tiling, | |
1723 | + unsigned int width, | |
1724 | + unsigned int height, | |
1725 | + unsigned int pitch, | |
1726 | + uint64_t base_offset, | |
1727 | + unsigned int y_offset) | |
1728 | +{ | |
1729 | + memset(ss, 0, sizeof(*ss)); | |
1730 | + | |
1731 | + /* Always set 1(align 4 mode) */ | |
1732 | + ss->ss0.vertical_alignment = 1; | |
1733 | + ss->ss0.horizontal_alignment = 1; | |
1734 | + | |
1735 | + ss->ss0.surface_format = format; | |
1736 | + ss->ss0.surface_type = I965_SURFACE_2D; | |
1737 | + | |
1738 | + ss->ss1.surface_mocs = cacheability_control; | |
1739 | + | |
1740 | + ss->ss2.width = width - 1; | |
1741 | + ss->ss2.height = height - 1; | |
1742 | + | |
1743 | + ss->ss3.pitch = pitch - 1; | |
1744 | + | |
1745 | + ss->ss5.y_offset = y_offset; | |
1746 | + | |
1747 | + ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; | |
1748 | + ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE; | |
1749 | + ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN; | |
1750 | + ss->ss7.shader_chanel_select_r = HSW_SCS_RED; | |
1751 | + | |
1752 | + ss->ss8.base_addr = (uint32_t)base_offset; | |
1753 | + ss->ss9.base_addr_high = (uint32_t)(base_offset >> 32); | |
1754 | + | |
1755 | + gen9_gpe_set_surface_tiling(ss, tiling); | |
1756 | +} | |
1757 | + | |
1758 | +/* This is only for NV12 format */ | |
1759 | +static void | |
1760 | +gen9_gpe_set_adv_surface_state(struct gen9_surface_state2 *ss, | |
1761 | + unsigned int v_direction, | |
1762 | + unsigned int cacheability_control, | |
1763 | + unsigned int format, | |
1764 | + unsigned int tiling, | |
1765 | + unsigned int width, | |
1766 | + unsigned int height, | |
1767 | + unsigned int pitch, | |
1768 | + uint64_t base_offset, | |
1769 | + unsigned int y_cb_offset) | |
1770 | +{ | |
1771 | + memset(ss, 0, sizeof(*ss)); | |
1772 | + | |
1773 | + ss->ss1.cbcr_pixel_offset_v_direction = v_direction; | |
1774 | + ss->ss1.width = width - 1; | |
1775 | + ss->ss1.height = height - 1; | |
1776 | + | |
1777 | + ss->ss2.surface_format = format; | |
1778 | + ss->ss2.interleave_chroma = 1; | |
1779 | + ss->ss2.pitch = pitch - 1; | |
1780 | + | |
1781 | + ss->ss3.y_offset_for_cb = y_cb_offset; | |
1782 | + | |
1783 | + ss->ss5.surface_object_mocs = cacheability_control; | |
1784 | + | |
1785 | + ss->ss6.base_addr = (uint32_t)base_offset; | |
1786 | + ss->ss7.base_addr_high = (uint32_t)(base_offset >> 32); | |
1787 | + | |
1788 | + gen9_gpe_set_surface2_tiling(ss, tiling); | |
1789 | +} | |
1790 | + | |
1791 | +static void | |
1792 | +gen9_gpe_set_buffer2_surface_state(struct gen9_surface_state *ss, | |
1793 | + unsigned int cacheability_control, | |
1794 | + unsigned int format, | |
1795 | + unsigned int size, | |
1796 | + unsigned int pitch, | |
1797 | + uint64_t base_offset) | |
1798 | +{ | |
1799 | + memset(ss, 0, sizeof(*ss)); | |
1800 | + | |
1801 | + ss->ss0.surface_format = format; | |
1802 | + ss->ss0.surface_type = I965_SURFACE_BUFFER; | |
1803 | + | |
1804 | + ss->ss1.surface_mocs = cacheability_control; | |
1805 | + | |
1806 | + ss->ss2.width = (size - 1) & 0x7F; | |
1807 | + ss->ss2.height = ((size - 1) & 0x1FFF80) >> 7; | |
1808 | + | |
1809 | + ss->ss3.depth = ((size - 1) & 0xFE00000) >> 21; | |
1810 | + ss->ss3.pitch = pitch - 1; | |
1811 | + | |
1812 | + ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; | |
1813 | + ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE; | |
1814 | + ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN; | |
1815 | + ss->ss7.shader_chanel_select_r = HSW_SCS_RED; | |
1816 | + | |
1817 | + ss->ss8.base_addr = (uint32_t)base_offset; | |
1818 | + ss->ss9.base_addr_high = (uint32_t)(base_offset >> 32); | |
1819 | +} | |
1820 | + | |
1821 | +void | |
1822 | +gen9_gpe_context_add_surface(struct i965_gpe_context *gpe_context, | |
1823 | + struct i965_gpe_surface *gpe_surface, | |
1824 | + int index) | |
1825 | +{ | |
1826 | + char *buf; | |
1827 | + unsigned int tiling, swizzle, width, height, pitch, tile_alignment, y_offset = 0; | |
1828 | + unsigned int surface_state_offset = gpe_context->surface_state_binding_table.surface_state_offset + | |
1829 | + index * SURFACE_STATE_PADDED_SIZE_GEN9; | |
1830 | + unsigned int binding_table_offset = gpe_context->surface_state_binding_table.binding_table_offset + | |
1831 | + index * 4; | |
1832 | + struct i965_gpe_resource *gpe_resource = gpe_surface->gpe_resource; | |
1833 | + | |
1834 | + dri_bo_get_tiling(gpe_resource->bo, &tiling, &swizzle); | |
1835 | + | |
1836 | + dri_bo_map(gpe_context->surface_state_binding_table.bo, 1); | |
1837 | + buf = (char *)gpe_context->surface_state_binding_table.bo->virtual; | |
1838 | + *((unsigned int *)(buf + binding_table_offset)) = surface_state_offset; | |
1839 | + | |
1840 | + if (gpe_surface->is_2d_surface && gpe_surface->is_uv_surface) { | |
1841 | + unsigned int cbcr_offset; | |
1842 | + struct gen9_surface_state *ss = (struct gen9_surface_state *)(buf + surface_state_offset); | |
1843 | + | |
1844 | + width = gpe_resource->width; | |
1845 | + height = gpe_resource->height / 2; | |
1846 | + pitch = gpe_resource->pitch; | |
1847 | + | |
1848 | + if (gpe_surface->is_media_block_rw) | |
1849 | + width = (ALIGN(width, 4) >> 2); | |
1850 | + | |
1851 | + if (tiling == I915_TILING_Y) { | |
1852 | + tile_alignment = 32; | |
1853 | + } else if (tiling == I915_TILING_X) { | |
1854 | + tile_alignment = 8; | |
1855 | + } else | |
1856 | + tile_alignment = 1; | |
1857 | + | |
1858 | + y_offset = (gpe_resource->y_cb_offset % tile_alignment); | |
1859 | + cbcr_offset = ALIGN_FLOOR(gpe_resource->y_cb_offset, tile_alignment) * pitch; | |
1860 | + | |
1861 | + gen9_gpe_set_2d_surface_state(ss, | |
1862 | + gpe_surface->cacheability_control, | |
1863 | + I965_SURFACEFORMAT_R16_UINT, | |
1864 | + tiling, | |
1865 | + width, height, pitch, | |
1866 | + gpe_resource->bo->offset64 + cbcr_offset, | |
1867 | + y_offset); | |
1868 | + | |
1869 | + dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo, | |
1870 | + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, | |
1871 | + cbcr_offset, | |
1872 | + surface_state_offset + offsetof(struct gen9_surface_state, ss8), | |
1873 | + gpe_resource->bo); | |
1874 | + } else if (gpe_surface->is_2d_surface) { | |
1875 | + struct gen9_surface_state *ss = (struct gen9_surface_state *)(buf + surface_state_offset); | |
1876 | + | |
1877 | + width = gpe_resource->width; | |
1878 | + height = gpe_resource->height; | |
1879 | + pitch = gpe_resource->pitch; | |
1880 | + | |
1881 | + if (gpe_surface->is_media_block_rw) | |
1882 | + width = (ALIGN(width, 4) >> 2); | |
1883 | + | |
1884 | + gen9_gpe_set_2d_surface_state(ss, | |
1885 | + gpe_surface->cacheability_control, | |
1886 | + gpe_surface->format, | |
1887 | + tiling, | |
1888 | + width, height, pitch, | |
1889 | + gpe_resource->bo->offset64, | |
1890 | + y_offset); | |
1891 | + | |
1892 | + dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo, | |
1893 | + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, | |
1894 | + 0, | |
1895 | + surface_state_offset + offsetof(struct gen9_surface_state, ss8), | |
1896 | + gpe_resource->bo); | |
1897 | + } else if (gpe_surface->is_adv_surface) { | |
1898 | + struct gen9_surface_state2 *ss = (struct gen9_surface_state2 *)(buf + surface_state_offset); | |
1899 | + | |
1900 | + width = gpe_resource->width; | |
1901 | + height = gpe_resource->height; | |
1902 | + pitch = gpe_resource->pitch; | |
1903 | + | |
1904 | + gen9_gpe_set_adv_surface_state(ss, | |
1905 | + gpe_surface->v_direction, | |
1906 | + gpe_surface->cacheability_control, | |
1907 | + MFX_SURFACE_PLANAR_420_8, | |
1908 | + tiling, | |
1909 | + width, height, pitch, | |
1910 | + gpe_resource->bo->offset64, | |
1911 | + gpe_resource->y_cb_offset); | |
1912 | + | |
1913 | + dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo, | |
1914 | + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, | |
1915 | + 0, | |
1916 | + surface_state_offset + offsetof(struct gen9_surface_state2, ss6), | |
1917 | + gpe_resource->bo); | |
1918 | + } else { | |
1919 | + struct gen9_surface_state *ss = (struct gen9_surface_state *)(buf + surface_state_offset); | |
1920 | + unsigned int format; | |
1921 | + | |
1922 | + assert(gpe_surface->is_buffer); | |
1923 | + | |
1924 | + if (gpe_surface->is_raw_buffer) { | |
1925 | + format = I965_SURFACEFORMAT_RAW; | |
1926 | + pitch = 1; | |
1927 | + } else { | |
1928 | + format = I965_SURFACEFORMAT_R32_UINT; | |
1929 | + pitch = sizeof(unsigned int); | |
1930 | + } | |
1931 | + | |
1932 | + gen9_gpe_set_buffer2_surface_state(ss, | |
1933 | + gpe_surface->cacheability_control, | |
1934 | + format, | |
1935 | + gpe_surface->size, | |
1936 | + pitch, | |
1937 | + gpe_resource->bo->offset64 + gpe_surface->offset); | |
1938 | + | |
1939 | + dri_bo_emit_reloc(gpe_context->surface_state_binding_table.bo, | |
1940 | + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, | |
1941 | + gpe_surface->offset, | |
1942 | + surface_state_offset + offsetof(struct gen9_surface_state, ss8), | |
1943 | + gpe_resource->bo); | |
1944 | + } | |
1945 | + | |
1946 | + dri_bo_unmap(gpe_context->surface_state_binding_table.bo); | |
1947 | +} | |
1948 | + | |
1949 | +bool | |
1950 | +i965_gpe_allocate_2d_resource(dri_bufmgr *bufmgr, | |
1951 | + struct i965_gpe_resource *res, | |
1952 | + int width, | |
1953 | + int height, | |
1954 | + int pitch, | |
1955 | + const char *name) | |
1956 | +{ | |
1957 | + int bo_size; | |
1958 | + | |
1959 | + if (!res) | |
1960 | + return false; | |
1961 | + | |
1962 | + res->type = I965_GPE_RESOURCE_2D; | |
1963 | + res->width = width; | |
1964 | + res->height = height; | |
1965 | + res->pitch = pitch; | |
1966 | + | |
1967 | + bo_size = ALIGN(height, 16) * pitch; | |
1968 | + res->size = bo_size; | |
1969 | + | |
1970 | + res->bo = dri_bo_alloc(bufmgr, name, res->size, 4096); | |
1971 | + res->map = NULL; | |
1972 | + | |
1973 | + return true; | |
1974 | +} | |
1975 | + | |
1976 | +void | |
1977 | +gen8_gpe_media_state_flush(VADriverContextP ctx, | |
1978 | + struct i965_gpe_context *gpe_context, | |
1979 | + struct intel_batchbuffer *batch) | |
1980 | +{ | |
1981 | + BEGIN_BATCH(batch, 2); | |
1982 | + | |
1983 | + OUT_BATCH(batch, CMD_MEDIA_STATE_FLUSH | (2 - 2)); | |
1984 | + OUT_BATCH(batch, 0); | |
1985 | + | |
1986 | + ADVANCE_BATCH(batch); | |
1987 | +} | |
1988 | + | |
1989 | +void | |
1990 | +gen8_gpe_media_object(VADriverContextP ctx, | |
1991 | + struct i965_gpe_context *gpe_context, | |
1992 | + struct intel_batchbuffer *batch, | |
1993 | + struct gpe_media_object_parameter *param) | |
1994 | +{ | |
1995 | + int batch_size, subdata_size; | |
1996 | + | |
1997 | + batch_size = 6; | |
1998 | + subdata_size = 0; | |
1999 | + if (param->pinline_data && param->inline_size) { | |
2000 | + subdata_size = ALIGN(param->inline_size, 4); | |
2001 | + batch_size += subdata_size / 4; | |
2002 | + } | |
2003 | + BEGIN_BATCH(batch, batch_size); | |
2004 | + OUT_BATCH(batch, CMD_MEDIA_OBJECT | (batch_size - 2)); | |
2005 | + OUT_BATCH(batch, param->interface_offset); | |
2006 | + OUT_BATCH(batch, param->use_scoreboard << 21); | |
2007 | + OUT_BATCH(batch, 0); | |
2008 | + OUT_BATCH(batch, (param->scoreboard_y << 16 | | |
2009 | + param->scoreboard_x)); | |
2010 | + OUT_BATCH(batch, param->scoreboard_mask); | |
2011 | + | |
2012 | + if (subdata_size) | |
2013 | + intel_batchbuffer_data(batch, param->pinline_data, subdata_size); | |
2014 | + | |
2015 | + ADVANCE_BATCH(batch); | |
2016 | +} | |
2017 | + | |
2018 | +void | |
2019 | +gen9_gpe_media_object_walker(VADriverContextP ctx, | |
2020 | + struct i965_gpe_context *gpe_context, | |
2021 | + struct intel_batchbuffer *batch, | |
2022 | + struct gpe_media_object_walker_parameter *param) | |
2023 | +{ | |
2024 | + int walker_length; | |
2025 | + | |
2026 | + walker_length = 17; | |
2027 | + if (param->inline_size) | |
2028 | + walker_length += ALIGN(param->inline_size, 4) / 4; | |
2029 | + BEGIN_BATCH(batch, walker_length); | |
2030 | + OUT_BATCH(batch, CMD_MEDIA_OBJECT_WALKER | (walker_length - 2)); | |
2031 | + OUT_BATCH(batch, param->interface_offset); | |
2032 | + OUT_BATCH(batch, param->use_scoreboard << 21); | |
2033 | + OUT_BATCH(batch, 0); | |
2034 | + OUT_BATCH(batch, 0); | |
2035 | + OUT_BATCH(batch, (param->group_id_loop_select << 8 | | |
2036 | + param->scoreboard_mask)); // DW5 | |
2037 | + OUT_BATCH(batch, (param->color_count_minus1 << 24 | | |
2038 | + param->middle_loop_extra_steps << 16 | | |
2039 | + param->mid_loop_unit_y << 12 | | |
2040 | + param->mid_loop_unit_x << 8)); | |
2041 | + OUT_BATCH(batch, ((param->global_loop_exec_count & 0x3ff) << 16 | | |
2042 | + (param->local_loop_exec_count & 0x3ff))); | |
2043 | + OUT_BATCH(batch, param->block_resolution.value); | |
2044 | + OUT_BATCH(batch, param->local_start.value); | |
2045 | + OUT_BATCH(batch, 0); // DW10 | |
2046 | + OUT_BATCH(batch, param->local_outer_loop_stride.value); | |
2047 | + OUT_BATCH(batch, param->local_inner_loop_unit.value); | |
2048 | + OUT_BATCH(batch, param->global_resolution.value); | |
2049 | + OUT_BATCH(batch, param->global_start.value); | |
2050 | + OUT_BATCH(batch, param->global_outer_loop_stride.value); | |
2051 | + OUT_BATCH(batch, param->global_inner_loop_unit.value); | |
2052 | + | |
2053 | + if (param->pinline_data && param->inline_size) | |
2054 | + intel_batchbuffer_data(batch, param->pinline_data, ALIGN(param->inline_size, 4)); | |
2055 | + | |
2056 | + ADVANCE_BATCH(batch); | |
2057 | +} |
@@ -78,6 +78,9 @@ struct i965_gpe_context | ||
78 | 78 | struct { |
79 | 79 | dri_bo *bo; |
80 | 80 | unsigned int length; /* in bytes */ |
81 | + unsigned int max_entries; | |
82 | + unsigned int binding_table_offset; | |
83 | + unsigned int surface_state_offset; | |
81 | 84 | } surface_state_binding_table; |
82 | 85 | |
83 | 86 | struct { |
@@ -161,6 +164,7 @@ struct i965_gpe_context | ||
161 | 164 | } dynamic_state; |
162 | 165 | |
163 | 166 | unsigned int sampler_offset; |
167 | + int sampler_entries; | |
164 | 168 | int sampler_size; |
165 | 169 | unsigned int idrt_offset; |
166 | 170 | int idrt_size; |
@@ -329,6 +333,7 @@ void gen9_gpe_pipeline_end(VADriverContextP ctx, | ||
329 | 333 | |
330 | 334 | Bool i965_allocate_gpe_resource(dri_bufmgr *bufmgr, |
331 | 335 | struct i965_gpe_resource *res, |
336 | + int size, | |
332 | 337 | const char *name); |
333 | 338 | |
334 | 339 | void i965_object_surface_to_2d_gpe_resource(struct i965_gpe_resource *res, |
@@ -387,4 +392,114 @@ void gen9_gpe_mi_batch_buffer_start(VADriverContextP ctx, | ||
387 | 392 | struct intel_batchbuffer *batch, |
388 | 393 | struct gpe_mi_batch_buffer_start_parameter *params); |
389 | 394 | |
395 | + | |
396 | +struct gpe_media_object_parameter | |
397 | +{ | |
398 | + unsigned int use_scoreboard; | |
399 | + unsigned int scoreboard_x; | |
400 | + unsigned int scoreboard_y; | |
401 | + unsigned int scoreboard_mask; | |
402 | + unsigned int interface_offset; | |
403 | + void *pinline_data; | |
404 | + unsigned int inline_size; | |
405 | +}; | |
406 | + | |
407 | +struct i965_gpe_surface | |
408 | +{ | |
409 | + unsigned int is_buffer:1; | |
410 | + unsigned int is_2d_surface:1; | |
411 | + unsigned int is_adv_surface:1; | |
412 | + unsigned int is_uv_surface:1; | |
413 | + unsigned int is_media_block_rw:1; | |
414 | + unsigned int is_raw_buffer:1; | |
415 | + | |
416 | + unsigned int vert_line_stride_offset; | |
417 | + unsigned int vert_line_stride; | |
418 | + unsigned int cacheability_control; | |
419 | + unsigned int format; // 2d surface only | |
420 | + unsigned int v_direction; // adv surface only | |
421 | + unsigned int size; // buffer only | |
422 | + unsigned int offset; // buffer only | |
423 | + | |
424 | + struct i965_gpe_resource *gpe_resource; | |
425 | +}; | |
426 | + | |
427 | +extern void | |
428 | +gen9_gpe_reset_binding_table(VADriverContextP ctx, | |
429 | + struct i965_gpe_context *gpe_context); | |
430 | +extern | |
431 | +void *gen8p_gpe_context_map_curbe(struct i965_gpe_context *gpe_context); | |
432 | + | |
433 | +extern | |
434 | +void gen8p_gpe_context_unmap_curbe(struct i965_gpe_context *gpe_context); | |
435 | + | |
436 | +extern | |
437 | +void gen8_gpe_setup_interface_data(VADriverContextP ctx, | |
438 | + struct i965_gpe_context *gpe_context); | |
439 | +extern void | |
440 | +gen9_gpe_context_add_surface(struct i965_gpe_context *gpe_context, | |
441 | + struct i965_gpe_surface *gpe_surface, | |
442 | + int index); | |
443 | + | |
444 | +extern bool | |
445 | +i965_gpe_allocate_2d_resource(dri_bufmgr *bufmgr, | |
446 | + struct i965_gpe_resource *res, | |
447 | + int width, | |
448 | + int height, | |
449 | + int pitch, | |
450 | + const char *name); | |
451 | + | |
452 | +struct gpe_walker_xy | |
453 | +{ | |
454 | + union { | |
455 | + struct { | |
456 | + unsigned int x:16; | |
457 | + unsigned int y:16; | |
458 | + }; | |
459 | + unsigned int value; | |
460 | + }; | |
461 | +}; | |
462 | + | |
463 | +struct gpe_media_object_walker_parameter | |
464 | +{ | |
465 | + void *pinline_data; | |
466 | + unsigned int inline_size; | |
467 | + unsigned int interface_offset; | |
468 | + unsigned int use_scoreboard; | |
469 | + unsigned int scoreboard_mask; | |
470 | + unsigned int group_id_loop_select; | |
471 | + unsigned int color_count_minus1; | |
472 | + unsigned int mid_loop_unit_x; | |
473 | + unsigned int mid_loop_unit_y; | |
474 | + unsigned int middle_loop_extra_steps; | |
475 | + unsigned int local_loop_exec_count; | |
476 | + unsigned int global_loop_exec_count; | |
477 | + struct gpe_walker_xy block_resolution; | |
478 | + struct gpe_walker_xy local_start; | |
479 | + struct gpe_walker_xy local_end; | |
480 | + struct gpe_walker_xy local_outer_loop_stride; | |
481 | + struct gpe_walker_xy local_inner_loop_unit; | |
482 | + struct gpe_walker_xy global_resolution; | |
483 | + struct gpe_walker_xy global_start; | |
484 | + struct gpe_walker_xy global_outer_loop_stride; | |
485 | + struct gpe_walker_xy global_inner_loop_unit; | |
486 | +}; | |
487 | + | |
488 | +extern void | |
489 | +gen8_gpe_media_object(VADriverContextP ctx, | |
490 | + struct i965_gpe_context *gpe_context, | |
491 | + struct intel_batchbuffer *batch, | |
492 | + struct gpe_media_object_parameter *param); | |
493 | + | |
494 | +extern void | |
495 | +gen8_gpe_media_state_flush(VADriverContextP ctx, | |
496 | + struct i965_gpe_context *gpe_context, | |
497 | + struct intel_batchbuffer *batch); | |
498 | + | |
499 | +extern void | |
500 | +gen9_gpe_media_object_walker(VADriverContextP ctx, | |
501 | + struct i965_gpe_context *gpe_context, | |
502 | + struct intel_batchbuffer *batch, | |
503 | + struct gpe_media_object_walker_parameter *param); | |
504 | + | |
390 | 505 | #endif /* _I965_GPE_UTILS_H_ */ |
@@ -92,6 +92,8 @@ struct intel_batchbuffer; | ||
92 | 92 | #define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0])) |
93 | 93 | #define CLAMP(min, max, a) ((a) < (min) ? (min) : ((a) > (max) ? (max) : (a))) |
94 | 94 | |
95 | +#define ALIGN_FLOOR(i, n) ((i) & ~((n) - 1)) | |
96 | + | |
95 | 97 | #define Bool int |
96 | 98 | #define True 1 |
97 | 99 | #define False 0 |