hardware/intel/intel-driver
Revisión | e889cefebad2a2fa2230882b8070309f23054247 (tree) |
---|---|
Tiempo | 2014-05-26 12:59:24 |
Autor | Xiang, Haihao <haihao.xiang@inte...> |
Commiter | Xiang, Haihao |
Remove max_wm_threads from render_state
Instead directly use the value stored in intel_device_info
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 6ba787b29e4bcebdceda52906e33cb84f24a63b5)
@@ -1377,7 +1377,7 @@ gen8_emit_wm_state(VADriverContextP ctx, int kernel) | ||
1377 | 1377 | unsigned int num_samples = 0; |
1378 | 1378 | unsigned int max_threads; |
1379 | 1379 | |
1380 | - max_threads = render_state->max_wm_threads - 2; | |
1380 | + max_threads = i965->intel.device_info->max_wm_threads - 2; | |
1381 | 1381 | |
1382 | 1382 | BEGIN_BATCH(batch, 2); |
1383 | 1383 | OUT_BATCH(batch, GEN8_3DSTATE_PSEXTRA | (2 - 2)); |
@@ -1784,14 +1784,6 @@ gen8_render_init(VADriverContextP ctx) | ||
1784 | 1784 | |
1785 | 1785 | dri_bo_unmap(render_state->instruction_state.bo); |
1786 | 1786 | |
1787 | - | |
1788 | - if (IS_GEN8(i965->intel.device_id)) { | |
1789 | - render_state->max_wm_threads = 64; | |
1790 | - } else { | |
1791 | - /* should never get here !!! */ | |
1792 | - assert(0); | |
1793 | - } | |
1794 | - | |
1795 | 1787 | return true; |
1796 | 1788 | } |
1797 | 1789 |
@@ -478,7 +478,7 @@ i965_subpic_render_wm_unit(VADriverContextP ctx) | ||
478 | 478 | wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4; |
479 | 479 | } |
480 | 480 | |
481 | - wm_state->wm5.max_threads = render_state->max_wm_threads - 1; | |
481 | + wm_state->wm5.max_threads = i965->intel.device_info->max_wm_threads - 1; | |
482 | 482 | wm_state->wm5.thread_dispatch_enable = 1; |
483 | 483 | wm_state->wm5.enable_16_pix = 1; |
484 | 484 | wm_state->wm5.enable_8_pix = 0; |
@@ -542,7 +542,7 @@ i965_render_wm_unit(VADriverContextP ctx) | ||
542 | 542 | wm_state->wm4.sampler_count = (render_state->wm.sampler_count + 3) / 4; |
543 | 543 | } |
544 | 544 | |
545 | - wm_state->wm5.max_threads = render_state->max_wm_threads - 1; | |
545 | + wm_state->wm5.max_threads = i965->intel.device_info->max_wm_threads - 1; | |
546 | 546 | wm_state->wm5.thread_dispatch_enable = 1; |
547 | 547 | wm_state->wm5.enable_16_pix = 1; |
548 | 548 | wm_state->wm5.enable_8_pix = 0; |
@@ -2117,7 +2117,7 @@ gen6_emit_wm_state(VADriverContextP ctx, int kernel) | ||
2117 | 2117 | (5 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT)); |
2118 | 2118 | OUT_BATCH(batch, 0); |
2119 | 2119 | OUT_BATCH(batch, (6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */ |
2120 | - OUT_BATCH(batch, ((render_state->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) | | |
2120 | + OUT_BATCH(batch, ((i965->intel.device_info->max_wm_threads - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) | | |
2121 | 2121 | GEN6_3DSTATE_WM_DISPATCH_ENABLE | |
2122 | 2122 | GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); |
2123 | 2123 | OUT_BATCH(batch, (1 << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) | |
@@ -2899,7 +2899,7 @@ gen7_emit_wm_state(VADriverContextP ctx, int kernel) | ||
2899 | 2899 | (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); |
2900 | 2900 | OUT_BATCH(batch, 0); /* scratch space base offset */ |
2901 | 2901 | OUT_BATCH(batch, |
2902 | - ((render_state->max_wm_threads - 1) << max_threads_shift) | num_samples | | |
2902 | + ((i965->intel.device_info->max_wm_threads - 1) << max_threads_shift) | num_samples | | |
2903 | 2903 | GEN7_PS_PUSH_CONSTANT_ENABLE | |
2904 | 2904 | GEN7_PS_ATTRIBUTE_ENABLE | |
2905 | 2905 | GEN7_PS_16_DISPATCH_ENABLE); |
@@ -3187,29 +3187,6 @@ i965_render_init(VADriverContextP ctx) | ||
3187 | 3187 | 4096, 64); |
3188 | 3188 | assert(render_state->curbe.bo); |
3189 | 3189 | |
3190 | - if (IS_HSW_GT1(i965->intel.device_id)) { | |
3191 | - render_state->max_wm_threads = 102; | |
3192 | - } else if (IS_HSW_GT2(i965->intel.device_id)) { | |
3193 | - render_state->max_wm_threads = 204; | |
3194 | - } else if (IS_HSW_GT3(i965->intel.device_id)) { | |
3195 | - render_state->max_wm_threads = 408; | |
3196 | - } else if (IS_IVB_GT1(i965->intel.device_id) || IS_BAYTRAIL(i965->intel.device_id)) { | |
3197 | - render_state->max_wm_threads = 48; | |
3198 | - } else if (IS_IVB_GT2(i965->intel.device_id)) { | |
3199 | - render_state->max_wm_threads = 172; | |
3200 | - } else if (IS_SNB_GT1(i965->intel.device_id)) { | |
3201 | - render_state->max_wm_threads = 40; | |
3202 | - } else if (IS_SNB_GT2(i965->intel.device_id)) { | |
3203 | - render_state->max_wm_threads = 80; | |
3204 | - } else if (IS_IRONLAKE(i965->intel.device_id)) { | |
3205 | - render_state->max_wm_threads = 72; /* 12 * 6 */ | |
3206 | - } else if (IS_G4X(i965->intel.device_id)) { | |
3207 | - render_state->max_wm_threads = 50; /* 12 * 5 */ | |
3208 | - } else { | |
3209 | - /* should never get here !!! */ | |
3210 | - assert(0); | |
3211 | - } | |
3212 | - | |
3213 | 3190 | return true; |
3214 | 3191 | } |
3215 | 3192 |
@@ -79,8 +79,6 @@ struct i965_render_state | ||
79 | 79 | |
80 | 80 | struct i965_kernel render_kernels[3]; |
81 | 81 | |
82 | - int max_wm_threads; | |
83 | - | |
84 | 82 | struct { |
85 | 83 | dri_bo *bo; |
86 | 84 | int bo_size; |