TLS/SSL and crypto library
Revisión | d11e6a4410d5aae70ad545d085d344644c33d9cc (tree) |
---|---|
Tiempo | 2017-08-31 05:45:26 |
Autor | Steve Marquess <marquess@open...> |
Commiter | Dr. Stephen Henson |
Add linux-mips32be target for new platform
Reviewed-by: Rich Salz <rsalz@openssl.org>
Reviewed-by: Andy Polyakov <appro@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/3300)
(cherry picked from commit d674242a884368083bf1044cc4e6e30d8f452a50)
@@ -132,7 +132,9 @@ my $ia64_asm="ia64cpuid.o:bn-ia64.o ia64-mont.o::aes_core.o aes_cbc.o aes-ia64.o | ||
132 | 132 | my $sparcv9_asm="sparcv9cap.o sparccpuid.o:bn-sparcv9.o sparcv9-mont.o sparcv9a-mont.o:des_enc-sparc.o fcrypt_b.o:aes_core.o aes_cbc.o aes-sparcv9.o:::sha1-sparcv9.o sha256-sparcv9.o sha512-sparcv9.o:::::::ghash-sparcv9.o::void"; |
133 | 133 | my $sparcv8_asm=":sparcv8.o:des_enc-sparc.o fcrypt_b.o:::::::::::::void"; |
134 | 134 | my $alpha_asm="alphacpuid.o:bn_asm.o alpha-mont.o:::::sha1-alpha.o:::::::ghash-alpha.o::void"; |
135 | -my $mips32_asm=":bn-mips.o::aes_cbc.o aes-mips.o:::sha1-mips.o sha256-mips.o::::::::"; | |
135 | +# EXTREME: original asm spec was missing colon and final term. | |
136 | +#my $mips32_asm=":bn-mips.o::aes_cbc.o aes-mips.o:::sha1-mips.o sha256-mips.o::::::::"; | |
137 | +my $mips32_asm=":bn-mips.o::aes_cbc.o aes-mips.o:::sha1-mips.o sha256-mips.o:::::::::void"; | |
136 | 138 | my $mips64_asm=":bn-mips.o mips-mont.o::aes_cbc.o aes-mips.o:::sha1-mips.o sha256-mips.o sha512-mips.o::::::::"; |
137 | 139 | my $s390x_asm="s390xcap.o s390xcpuid.o:bn-s390x.o s390x-mont.o s390x-gf2m.o::aes_ctr.o aes-s390x.o:::sha1-s390x.o sha256-s390x.o sha512-s390x.o::rc4-s390x.o:::::ghash-s390x.o:"; |
138 | 140 | my $armv4_asm="armcap.o armv4cpuid.o:bn_asm.o armv4-mont.o armv4-gf2m.o::aes_cbc.o aes-armv4.o:::sha1-armv4-large.o sha256-armv4.o sha512-armv4.o:::::::ghash-armv4.o::void"; |
@@ -342,6 +344,8 @@ my %table=( | ||
342 | 344 | # *-generic* is endian-neutral target, but ./config is free to |
343 | 345 | # throw in -D[BL]_ENDIAN, whichever appropriate... |
344 | 346 | "linux-generic32","gcc:-DTERMIO -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${no_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)", |
347 | +#### Extreme add linux-mips32be | |
348 | +"linux-mips32be","gcc:-DB_ENDIAN -DTERMIO -O3 -march=mips32 -fomit-frame-pointer -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${mips32_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)", | |
345 | 349 | "linux-ppc", "gcc:-DB_ENDIAN -DTERMIO -O3 -Wall::-D_REENTRANT::-ldl:BN_LLONG RC4_CHAR RC4_CHUNK DES_RISC1 DES_UNROLL:${ppc32_asm}:linux32:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)", |
346 | 350 | # It's believed that majority of ARM toolchains predefine appropriate -march. |
347 | 351 | # If you compiler does not, do complement config command line with one! |
@@ -555,6 +555,10 @@ case "$GUESSOS" in | ||
555 | 555 | #fi |
556 | 556 | OUT="irix-mips3-$CC" |
557 | 557 | ;; |
558 | + mips32be-*-linux2) | |
559 | + OUT=linux-mips32be | |
560 | + options="$options threads shared zlib-dynamic" | |
561 | + ;; | |
558 | 562 | ppc-apple-rhapsody) OUT="rhapsody-ppc-cc" ;; |
559 | 563 | ppc-apple-darwin*) |
560 | 564 | ISA64=`(sysctl -n hw.optional.64bitops) 2>/dev/null` |