hardware/intel/common/vaapi
Revisión | 6702b01ee3598017f05374bfc7956493f790361c (tree) |
---|---|
Tiempo | 2017-07-28 13:52:07 |
Autor | carpalis <30320745+carpalis@user...> |
Commiter | Xiang, Haihao |
implement intensity compensation for VC-1 decoding
Intensity compensation was not present for B-frames, but only for P-frames. When a P-frame flags intensity compensation for its forward reference frame, all subsequent B-frames that use this reference frame as well, need to do intensity compensation as well.
@@ -1518,6 +1518,9 @@ gen75_mfd_init_vc1_surface(VADriverContextP ctx, | ||
1518 | 1518 | } |
1519 | 1519 | |
1520 | 1520 | gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type; |
1521 | + gen7_vc1_surface->intensity_compensation = 0; | |
1522 | + gen7_vc1_surface->luma_scale = 0; | |
1523 | + gen7_vc1_surface->luma_shift = 0; | |
1521 | 1524 | |
1522 | 1525 | if (gen7_vc1_surface->dmv == NULL) { |
1523 | 1526 | gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr, |
@@ -1538,17 +1541,33 @@ gen75_mfd_vc1_decode_init(VADriverContextP ctx, | ||
1538 | 1541 | dri_bo *bo; |
1539 | 1542 | int width_in_mbs; |
1540 | 1543 | int picture_type; |
1544 | + int intensity_compensation; | |
1541 | 1545 | |
1542 | 1546 | assert(decode_state->pic_param && decode_state->pic_param->buffer); |
1543 | 1547 | pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; |
1544 | 1548 | width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; |
1545 | 1549 | picture_type = pic_param->picture_fields.bits.picture_type; |
1550 | + intensity_compensation = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); | |
1546 | 1551 | |
1547 | 1552 | intel_update_vc1_frame_store_index(ctx, |
1548 | 1553 | decode_state, |
1549 | 1554 | pic_param, |
1550 | 1555 | gen7_mfd_context->reference_surface); |
1551 | 1556 | |
1557 | + /* Forward reference picture */ | |
1558 | + obj_surface = decode_state->reference_objects[0]; | |
1559 | + if (pic_param->forward_reference_picture != VA_INVALID_ID && | |
1560 | + obj_surface && | |
1561 | + obj_surface->private_data) { | |
1562 | + if (picture_type == 1 && intensity_compensation) { /* P picture */ | |
1563 | + struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data; | |
1564 | + | |
1565 | + gen7_vc1_surface->intensity_compensation = intensity_compensation; | |
1566 | + gen7_vc1_surface->luma_scale = pic_param->luma_scale; | |
1567 | + gen7_vc1_surface->luma_shift = pic_param->luma_shift; | |
1568 | + } | |
1569 | + } | |
1570 | + | |
1552 | 1571 | /* Current decoded picture */ |
1553 | 1572 | obj_surface = decode_state->render_object; |
1554 | 1573 | i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420); |
@@ -1915,24 +1934,37 @@ gen75_mfd_vc1_pred_pipe_state(VADriverContextP ctx, | ||
1915 | 1934 | { |
1916 | 1935 | struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; |
1917 | 1936 | VAPictureParameterBufferVC1 *pic_param; |
1918 | - int intensitycomp_single; | |
1937 | + int picture_type; | |
1938 | + int intensitycomp_single_fwd = 0; | |
1939 | + int luma_scale1 = 0; | |
1940 | + int luma_shift1 = 0; | |
1919 | 1941 | |
1920 | 1942 | assert(decode_state->pic_param && decode_state->pic_param->buffer); |
1921 | 1943 | pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; |
1922 | - intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); | |
1944 | + picture_type = pic_param->picture_fields.bits.picture_type; | |
1945 | + | |
1946 | + if (gen7_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID) { | |
1947 | + if (picture_type == 1 || picture_type == 2) { /* P/B picture */ | |
1948 | + struct gen7_vc1_surface *gen7_vc1_surface = gen7_mfd_context->reference_surface[0].obj_surface->private_data; | |
1949 | + | |
1950 | + intensitycomp_single_fwd = gen7_vc1_surface->intensity_compensation; | |
1951 | + luma_scale1 = gen7_vc1_surface->luma_scale; | |
1952 | + luma_shift1 = gen7_vc1_surface->luma_shift; | |
1953 | + } | |
1954 | + } | |
1923 | 1955 | |
1924 | 1956 | BEGIN_BCS_BATCH(batch, 6); |
1925 | 1957 | OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2)); |
1926 | 1958 | OUT_BCS_BATCH(batch, |
1927 | 1959 | 0 << 14 | /* FIXME: double ??? */ |
1928 | 1960 | 0 << 12 | |
1929 | - intensitycomp_single << 10 | | |
1930 | - intensitycomp_single << 8 | | |
1961 | + intensitycomp_single_fwd << 10 | | |
1962 | + 0 << 8 | | |
1931 | 1963 | 0 << 4 | /* FIXME: interlace mode */ |
1932 | 1964 | 0); |
1933 | 1965 | OUT_BCS_BATCH(batch, |
1934 | - pic_param->luma_shift << 16 | | |
1935 | - pic_param->luma_scale << 0); /* FIXME: Luma Scaling */ | |
1966 | + luma_shift1 << 16 | | |
1967 | + luma_scale1 << 0); | |
1936 | 1968 | OUT_BCS_BATCH(batch, 0); |
1937 | 1969 | OUT_BCS_BATCH(batch, 0); |
1938 | 1970 | OUT_BCS_BATCH(batch, 0); |
@@ -1253,6 +1253,9 @@ gen7_mfd_init_vc1_surface(VADriverContextP ctx, | ||
1253 | 1253 | } |
1254 | 1254 | |
1255 | 1255 | gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type; |
1256 | + gen7_vc1_surface->intensity_compensation = 0; | |
1257 | + gen7_vc1_surface->luma_scale = 0; | |
1258 | + gen7_vc1_surface->luma_shift = 0; | |
1256 | 1259 | |
1257 | 1260 | if (gen7_vc1_surface->dmv == NULL) { |
1258 | 1261 | gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr, |
@@ -1273,17 +1276,33 @@ gen7_mfd_vc1_decode_init(VADriverContextP ctx, | ||
1273 | 1276 | dri_bo *bo; |
1274 | 1277 | int width_in_mbs; |
1275 | 1278 | int picture_type; |
1279 | + int intensity_compensation; | |
1276 | 1280 | |
1277 | 1281 | assert(decode_state->pic_param && decode_state->pic_param->buffer); |
1278 | 1282 | pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; |
1279 | 1283 | width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; |
1280 | 1284 | picture_type = pic_param->picture_fields.bits.picture_type; |
1285 | + intensity_compensation = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); | |
1281 | 1286 | |
1282 | 1287 | intel_update_vc1_frame_store_index(ctx, |
1283 | 1288 | decode_state, |
1284 | 1289 | pic_param, |
1285 | 1290 | gen7_mfd_context->reference_surface); |
1286 | 1291 | |
1292 | + /* Forward reference picture */ | |
1293 | + obj_surface = decode_state->reference_objects[0]; | |
1294 | + if (pic_param->forward_reference_picture != VA_INVALID_ID && | |
1295 | + obj_surface && | |
1296 | + obj_surface->private_data) { | |
1297 | + if (picture_type == 1 && intensity_compensation) { /* P picture */ | |
1298 | + struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data; | |
1299 | + | |
1300 | + gen7_vc1_surface->intensity_compensation = intensity_compensation; | |
1301 | + gen7_vc1_surface->luma_scale = pic_param->luma_scale; | |
1302 | + gen7_vc1_surface->luma_shift = pic_param->luma_shift; | |
1303 | + } | |
1304 | + } | |
1305 | + | |
1287 | 1306 | /* Current decoded picture */ |
1288 | 1307 | obj_surface = decode_state->render_object; |
1289 | 1308 | i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420); |
@@ -1650,24 +1669,37 @@ gen7_mfd_vc1_pred_pipe_state(VADriverContextP ctx, | ||
1650 | 1669 | { |
1651 | 1670 | struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; |
1652 | 1671 | VAPictureParameterBufferVC1 *pic_param; |
1653 | - int intensitycomp_single; | |
1672 | + int picture_type; | |
1673 | + int intensitycomp_single_fwd = 0; | |
1674 | + int luma_scale1 = 0; | |
1675 | + int luma_shift1 = 0; | |
1654 | 1676 | |
1655 | 1677 | assert(decode_state->pic_param && decode_state->pic_param->buffer); |
1656 | 1678 | pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; |
1657 | - intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); | |
1679 | + picture_type = pic_param->picture_fields.bits.picture_type; | |
1680 | + | |
1681 | + if (gen7_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID) { | |
1682 | + if (picture_type == 1 || picture_type == 2) { /* P/B picture */ | |
1683 | + struct gen7_vc1_surface *gen7_vc1_surface = gen7_mfd_context->reference_surface[0].obj_surface->private_data; | |
1684 | + | |
1685 | + intensitycomp_single_fwd = gen7_vc1_surface->intensity_compensation; | |
1686 | + luma_scale1 = gen7_vc1_surface->luma_scale; | |
1687 | + luma_shift1 = gen7_vc1_surface->luma_shift; | |
1688 | + } | |
1689 | + } | |
1658 | 1690 | |
1659 | 1691 | BEGIN_BCS_BATCH(batch, 6); |
1660 | 1692 | OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2)); |
1661 | 1693 | OUT_BCS_BATCH(batch, |
1662 | 1694 | 0 << 14 | /* FIXME: double ??? */ |
1663 | 1695 | 0 << 12 | |
1664 | - intensitycomp_single << 10 | | |
1665 | - intensitycomp_single << 8 | | |
1696 | + intensitycomp_single_fwd << 10 | | |
1697 | + 0 << 8 | | |
1666 | 1698 | 0 << 4 | /* FIXME: interlace mode */ |
1667 | 1699 | 0); |
1668 | 1700 | OUT_BCS_BATCH(batch, |
1669 | - pic_param->luma_shift << 16 | | |
1670 | - pic_param->luma_scale << 0); /* FIXME: Luma Scaling */ | |
1701 | + luma_shift1 << 16 | | |
1702 | + luma_scale1 << 0); | |
1671 | 1703 | OUT_BCS_BATCH(batch, 0); |
1672 | 1704 | OUT_BCS_BATCH(batch, 0); |
1673 | 1705 | OUT_BCS_BATCH(batch, 0); |
@@ -63,6 +63,9 @@ | ||
63 | 63 | struct gen7_vc1_surface { |
64 | 64 | dri_bo *dmv; |
65 | 65 | int picture_type; |
66 | + int intensity_compensation; | |
67 | + int luma_scale; | |
68 | + int luma_shift; | |
66 | 69 | }; |
67 | 70 | |
68 | 71 | struct hw_context; |
@@ -1297,6 +1297,9 @@ gen8_mfd_init_vc1_surface(VADriverContextP ctx, | ||
1297 | 1297 | } |
1298 | 1298 | |
1299 | 1299 | gen7_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type; |
1300 | + gen7_vc1_surface->intensity_compensation = 0; | |
1301 | + gen7_vc1_surface->luma_scale = 0; | |
1302 | + gen7_vc1_surface->luma_shift = 0; | |
1300 | 1303 | |
1301 | 1304 | if (gen7_vc1_surface->dmv == NULL) { |
1302 | 1305 | gen7_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr, |
@@ -1317,17 +1320,33 @@ gen8_mfd_vc1_decode_init(VADriverContextP ctx, | ||
1317 | 1320 | dri_bo *bo; |
1318 | 1321 | int width_in_mbs; |
1319 | 1322 | int picture_type; |
1323 | + int intensity_compensation; | |
1320 | 1324 | |
1321 | 1325 | assert(decode_state->pic_param && decode_state->pic_param->buffer); |
1322 | 1326 | pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; |
1323 | 1327 | width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16; |
1324 | 1328 | picture_type = pic_param->picture_fields.bits.picture_type; |
1329 | + intensity_compensation = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); | |
1325 | 1330 | |
1326 | 1331 | intel_update_vc1_frame_store_index(ctx, |
1327 | 1332 | decode_state, |
1328 | 1333 | pic_param, |
1329 | 1334 | gen7_mfd_context->reference_surface); |
1330 | 1335 | |
1336 | + /* Forward reference picture */ | |
1337 | + obj_surface = decode_state->reference_objects[0]; | |
1338 | + if (pic_param->forward_reference_picture != VA_INVALID_ID && | |
1339 | + obj_surface && | |
1340 | + obj_surface->private_data) { | |
1341 | + if (picture_type == 1 && intensity_compensation) { /* P picture */ | |
1342 | + struct gen7_vc1_surface *gen7_vc1_surface = obj_surface->private_data; | |
1343 | + | |
1344 | + gen7_vc1_surface->intensity_compensation = intensity_compensation; | |
1345 | + gen7_vc1_surface->luma_scale = pic_param->luma_scale; | |
1346 | + gen7_vc1_surface->luma_shift = pic_param->luma_shift; | |
1347 | + } | |
1348 | + } | |
1349 | + | |
1331 | 1350 | /* Current decoded picture */ |
1332 | 1351 | obj_surface = decode_state->render_object; |
1333 | 1352 | i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC_NV12, SUBSAMPLE_YUV420); |
@@ -1694,24 +1713,37 @@ gen8_mfd_vc1_pred_pipe_state(VADriverContextP ctx, | ||
1694 | 1713 | { |
1695 | 1714 | struct intel_batchbuffer *batch = gen7_mfd_context->base.batch; |
1696 | 1715 | VAPictureParameterBufferVC1 *pic_param; |
1697 | - int intensitycomp_single; | |
1716 | + int picture_type; | |
1717 | + int intensitycomp_single_fwd = 0; | |
1718 | + int luma_scale1 = 0; | |
1719 | + int luma_shift1 = 0; | |
1698 | 1720 | |
1699 | 1721 | assert(decode_state->pic_param && decode_state->pic_param->buffer); |
1700 | 1722 | pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer; |
1701 | - intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation); | |
1723 | + picture_type = pic_param->picture_fields.bits.picture_type; | |
1724 | + | |
1725 | + if (gen7_mfd_context->reference_surface[0].surface_id != VA_INVALID_ID) { | |
1726 | + if (picture_type == 1 || picture_type == 2) { /* P/B picture */ | |
1727 | + struct gen7_vc1_surface *gen7_vc1_surface = gen7_mfd_context->reference_surface[0].obj_surface->private_data; | |
1728 | + | |
1729 | + intensitycomp_single_fwd = gen7_vc1_surface->intensity_compensation; | |
1730 | + luma_scale1 = gen7_vc1_surface->luma_scale; | |
1731 | + luma_shift1 = gen7_vc1_surface->luma_shift; | |
1732 | + } | |
1733 | + } | |
1702 | 1734 | |
1703 | 1735 | BEGIN_BCS_BATCH(batch, 6); |
1704 | 1736 | OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (6 - 2)); |
1705 | 1737 | OUT_BCS_BATCH(batch, |
1706 | 1738 | 0 << 14 | /* FIXME: double ??? */ |
1707 | 1739 | 0 << 12 | |
1708 | - intensitycomp_single << 10 | | |
1709 | - intensitycomp_single << 8 | | |
1740 | + intensitycomp_single_fwd << 10 | | |
1741 | + 0 << 8 | | |
1710 | 1742 | 0 << 4 | /* FIXME: interlace mode */ |
1711 | 1743 | 0); |
1712 | 1744 | OUT_BCS_BATCH(batch, |
1713 | - pic_param->luma_shift << 16 | | |
1714 | - pic_param->luma_scale << 0); /* FIXME: Luma Scaling */ | |
1745 | + luma_shift1 << 16 | | |
1746 | + luma_scale1 << 0); | |
1715 | 1747 | OUT_BCS_BATCH(batch, 0); |
1716 | 1748 | OUT_BCS_BATCH(batch, 0); |
1717 | 1749 | OUT_BCS_BATCH(batch, 0); |