Commit: 1310ff8c398b9ba440430383dc9b9ea53ff00ac2 - binutils_gdb (git)

Commit MetaInfo

• Revisión: 1310ff8c398b9ba440430383dc9b9ea53ff00ac2 (tree)
• Tiempo: 2015-12-27 16:37:39
• Autor: Yoshinori Sato <ysato@user...>
• Commiter: Yoshinori Sato

Log Message

TPU simulation

Cambiar Resumen

• modified: sim/rx/mem.c

Diferencia incremental

--- a/sim/rx/mem.c
+++ b/sim/rx/mem.c
@@ -592,10 +592,21 @@ mem_get_content_type (int address)
 #define TMRI_CMB (1<<1)
 #define TMRI_OVF (1<<0)
 
+#define TPU_CH 6
+#define TPU_TSTR (tpubase[0])
+#define TPU_TCR(ch) (tpubase[(ch+1) * 0x10 + 0])
+#define TPU_TSR(ch) (tpubase[(ch+1) * 0x10 + 5])
+#define TPU_TCNTH(ch) (tpubase[(ch+1) * 0x10 + 7])
+#define TPU_TCNTL(ch) (tpubase[(ch+1) * 0x10 + 6])
+#define TPU_GRAH(ch) (tpubase[(ch+1) * 0x10 + 9])
+#define TPU_GRAL(ch) (tpubase[(ch+1) * 0x10 + 8])
+#define TPU_GRBH(ch) (tpubase[(ch+1) * 0x10 + 11])
+#define TPU_GRBL(ch) (tpubase[(ch+1) * 0x10 + 10])
+
 static unsigned char get_tmrisr(int ch)
 {
   unsigned char *irptr = rx_mem_ptr(IRADR(174 + ch * 3), MPA_READING);
-  unsigned char isr;
+  unsigned char isr = 0;
   unsigned int i;
   for (i = 0; i < 3; i++)
     {
@@ -757,6 +768,80 @@ cmt_update(int cycles_diff)
     }
 }
 
+static void 
+tpu_update(unsigned int cycles_diff)
+{
+  static int prescale[4]={1,4,16,64};
+  const int prescale_div[4]={1,4,16,64};
+  int tm, cnt, pcnt, gr, pulse;
+  unsigned char *tpubase = rx_mem_ptr(0x00088100, MPA_WRITING);
+
+  for (pcnt = 0; pcnt < 4; pcnt++) {
+    prescale[pcnt] -= cycles_diff;
+    pulse = -prescale[pcnt] / prescale_div[pcnt] + 1;
+    if (prescale[pcnt]<=0) 
+    {
+      /* input time pulse */
+      for(tm=0; tm < TPU_CH; tm++) {
+
+	/* Timer enable check */
+	if (!(TPU_TSTR & (1 << tm)))
+	  continue;
+
+	/* update counter */
+        if ((TPU_TCR(tm) & 0x0f) == pcnt)
+          {
+            cnt = ((TPU_TCNTH(tm) << 8) | TPU_TCNTL(tm));
+	    cnt += pulse;
+
+	    /* CNT overflow check */
+            if (cnt>=0x10000)
+              {
+		int cascade_low = tm % 3;
+                cnt -= 0x10000;
+		if (cascade_low == 2)
+		  {
+		    int cascade_high = tm - cascade_low + 1;
+		    if ((TPU_TCR(cascade_high) & 0x0f) == 0x0f)
+		      {
+			int cascade_cnt;
+			cascade_cnt = ((TPU_TCNTH(cascade_high) << 8) | 
+				       TPU_TCNTL(cascade_high));
+			cascade_cnt++;
+			TPU_TCNTH(cascade_high) = (cascade_cnt >> 8);
+			TPU_TCNTL(cascade_high) = cascade_cnt & 0xff;
+		      }
+		  }
+              }
+
+	    /* GRA compare match check*/
+	    gr = (TPU_GRAH(tm) << 8) | TPU_GRAL(tm);
+	    if (cnt >= gr)
+	      {
+		if ((TPU_TCR(tm) & 0xe0) == 0x20)
+		  cnt = 0;
+	      }
+
+	    /* GRB compare match check*/
+	    gr = (TPU_GRBH(tm) << 8) | TPU_GRBL(tm);
+	    if (cnt >= gr)
+	      {
+		if ((TPU_TCR(tm) & 0xe0) == 0x40)
+		  cnt = 0;
+	      }
+
+	    /* update TCNT */
+            TPU_TCNTH(tm) = (cnt >> 8);
+	    TPU_TCNTL(tm) = cnt & 0xff;
+          }
+
+      }
+      prescale[pcnt]+=prescale_div[pcnt];
+      /* update TSR */
+    }
+  }
+}
+
 #define SMR(ch) (scibase[(ch) * 8 + 0])
 #define BRR(ch) (scibase[(ch) * 8 + 1])
 #define SCR(ch) (scibase[(ch) * 8 + 2])
@@ -1117,6 +1202,7 @@ int io_simulation(cpupri)
   prev_pcycle = pcycles;
   tmr_update(3, pcycle_diff);
   cmt_update(pcycle_diff);
+  tpu_update(pcycle_diff);
   sci(pcycle_diff);
   return icu(cpupri);
 }