binutils_gdb

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Merge remote-tracking branch 'origin'

[ARM] Add support for thumb1 pcrop relocations.

To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
movs r3, #:upper8_15:#foo
lsls r3, #8
adds r3, #:upper0_7:#foo
lsls r3, #8
adds r3, #:lower8_15:#foo
lsls r3, #8
adds r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
4: 2300 movs r3, #0
4: R_ARM_THM_ALU_ABS_G3_NC foo
6: 021b lsls r3, r3, #8
8: 3300 adds r3, #0
8: R_ARM_THM_ALU_ABS_G2_NC foo
a: 021b lsls r3, r3, #8
c: 3300 adds r3, #0
c: R_ARM_THM_ALU_ABS_G1_NC foo
e: 021b lsls r3, r3, #8
10: 3300 adds r3, #0
10: R_ARM_THM_ALU_ABS_G0_NC foo

Automatic date update in version.in

[ARM] Enable CRC by default for ARMv8.1 and later.

ARMv8.1 includes CRC as a required extension but the +crc feature isn't
enabled by -march=armv8.1-a as it should be. This patch fixes that.

opcode/include
2015-12-15 Matthew Wahab <matthew.wahab@arm.com>

* arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
feature macro.
(ARM_ARCH_V8_2A): Likewise.

Change-Id: Id1fe0e6fa51dede19d61e1fd08e68628ea1b1e9e

Remove refernces to a non-existent silicon errata.

* doc/c-msp430.texi (MSP430 Options): Remove references to a
non-existent silicon errata.
* config/tc-msp430.c: Likewise.

Tweak gdb.trace/ftrace.exp for aarch64

Some tests are skipped on aarch64 unexpectedly because arg0exp isn't
set. This patch is to set arg0exp to "$x0" for aarch64.

gdb/testsuite:

2015-12-15 Yao Qi <yao.qi@linaro.org>

* gdb.trace/ftrace.exp: Set arg0exp to "$x0" if target
is aarch64*-*-*.

bfd: don't produce corrupt COFF symbol table due to long ELF file name symbols

The re-writing logic in _bfd_coff_final_link() overwrote the ".file"
part of the symbol table entry, due to not coping with the auxiliary
entry generated in all cases.

Note that while I would have wanted to add a test case,
(a) I didn't spot any one testing the base functionality here, and
(b) I wasn't able to figure out proper conditionals to use in e.g.
ld-elf/elf.exp to check for the necessary PE/PE+ support (which
varies by target).

Fix invalid left shift of negative value

Fix occurrences of left-shifting negative constants in C code.

sim/arm/ChangeLog:

* thumbemu.c (handle_T2_insn): Fix left shift of negative value.
* armemu.c (handle_v6_insn): Likewise.

sim/avr/ChangeLog:

* interp.c (sign_ext): Fix left shift of negative value.

sim/mips/ChangeLog:

* micromips.igen (process_isa_mode): Fix left shift of negative
value.

sim/msp430/ChangeLog:

* msp430-sim.c (get_op, put_op): Fix left shift of negative value.

sim/v850/ChangeLog:

* simops.c (v850_bins): Fix left shift of negative value.

Update the copyright notices in the affected files.

PR 19339
* elf-vxworks.h: Update copyright notice.
* elf-vxworks.c: Update copyright notice.
* elf-nacl.h: Update copyright notice.
* elf-nacl.c: Update copyright notice.

Add support for the MRS instruction to the AArch64 simulator.

* aarch64/simulator.c (system_get): New function. Provides read
access to the dczid system register.
(do_mrs): New function - implements the MRS instruction.
(dexSystem): Call do_mrs for the MRS instruction. Halt on
unimplemented system instructions.

Add support for RX V2 Instruction Set

binutils
* readelf.c(get_machine_flags): Add v2 flag.

gas
* config/rx-defs.h(rx_cpu_type): Add RXV2 type.
* config/tc-rx.c(cpu_type_list): New type lookup table.
(md_parse_option): Use lookup table for choose cpu.
(md_show_usage): Add rxv2 for mcpu option.
* doc/c-rx.texi: Likewise.
* config/rx-parse.y: Add v2 instructions and ACC register.
(rx_check_v2): check v2 type.

include/elf
* rx.h(E_FLAG_RX_V2): New RXv2 type.

include/opcode
* rx.h: Add new instructions.

opcoes
* rx-deocde.opc(rx_decode_opcode): Add new instructions pattern.
* rx-dis.c(register_name): Add new register.

gas/testsuite
* gas/rx/emaca.d: New.
* gas/rx/emaca.sm: New.
* gas/rx/emsba.d: New.
* gas/rx/emsba.sm: New.
* gas/rx/emula.d: New.
* gas/rx/emula.sm: New.
* gas/rx/fadd.d: Add new pattern.
* gas/rx/fadd.sm: Add new pattern.
* gas/rx/fmul.d: Add new pattern.
* gas/rx/fmul.sm: Add new pattern.
* gas/rx/fsqrt.d: New.
* gas/rx/fsqrt.sm: New.
* gas/rx/fsub.d: Add new pattern.
* gas/rx/fsub.sm: Add new pattern.
* gas/rx/ftou.d: New.
* gas/rx/ftou.sm: New.
* gas/rx/maclh.d: New.
* gas/rx/maclh.sm: New.
* gas/rx/maclo.d: Add new pattern.
* gas/rx/maclo.sm: Add new pattern.
* gas/rx/macros.inc: Add new register.
* gas/rx/movco.d: New.
* gas/rx/movco.sm: New.
* gas/rx/movli.d: New.
* gas/rx/movli.sm: New.
* gas/rx/msbhi.d: New.
* gas/rx/msbhi.sm: New.
* gas/rx/msblh.d: New.
* gas/rx/msblh.sm: New.
* gas/rx/msblo.d: New.
* gas/rx/msblo.sm: New.
* gas/rx/mullh.d: New.
* gas/rx/mullh.sm: New.
* gas/rx/mvfacgu.d: New.
* gas/rx/mvfacgu.sm: New.
* gas/rx/mvfachi.d: Add new pattern.
* gas/rx/mvfachi.sm: Add new pattern.
* gas/rx/mvfaclo.d: Add new pattern.
* gas/rx/mvfaclo.sm: Add new pattern.
* gas/rx/mvfacmi.d: Add new pattern.
* gas/rx/mvfacmi.sm: Add new pattern.
* gas/rx/mvfc.d: Add new pattern.
* gas/rx/mvtacgu.d: New.
* gas/rx/mvtacgu.sm: New.
* gas/rx/mvtc.d: Add new pattern.
* gas/rx/popc.d: Add new pattern.
* gas/rx/pushc.d: Add new pattern.
* gas/rx/racl.d: New.
* gas/rx/racl.sm: New.
* gas/rx/racw.d: Add new pattern.
* gas/rx/racw.sm: Add new pattern.
* gas/rx/rdacl.d: New.
* gas/rx/rdacl.sm: New.
* gas/rx/rdacw.d: New.
* gas/rx/rdacw.sm: New.
* gas/rx/rx.exp: Add option.
* gas/rx/stnz.d: Add new pattern.
* gas/rx/stnz.sm: Add new pattern.
* gas/rx/stz.d: Add new pattern.
* gas/rx/stz.sm: Add new pattern.
* gas/rx/utof.d: New.
* gas/rx/utof.sm: New.

Automatic date update in version.in

Check for readline support in gdb.base/history-duplicates.exp.

2015-12-14 Sandra Loosemore <sandra@codesourcery.com>

gdb/testsuite/
* gdb.base/history-duplicates.exp: Skip if no readline support.

Skip gdb.base/gdbinit-history.exp on remote hosts.

2015-12-14 Sandra Loosemore <sandra@codesourcery.com>

gdb/testsuite/
* gdb.base/gdbinit-history.exp: Skip for remote-host testing.

Skip gdb.base/gdbhistsize-history.exp on remote hosts.

2015-12-14 Sandra Loosemore <sandra@codesourcery.com>

gdb/testsuite/
* gdb.base/gdbhistsize-history.exp: Skip for remote-host testing.

Skip tests that send ctrl-c to GDB if nointerrupts target property is set.

2015-12-14 Sandra Loosemore <sandra@codesourcery.com>

gdb/testsuite/
* gdb.base/completion.exp: Skip tests that interrupt GDB with
ctrl-C if nointerrupts target property is set.
* gdb.base/double-prompt-target-event-error.exp: Likewise.
* gdb.base/paginate-after-ctrl-c-running.exp: Likewise.
* gdb.base/paginate-bg-execution.exp: Likewise.
* gdb.base/paginate-execution-startup.exp: Likewise.
* gdb.base/random-signal.exp: Likewise.
* gdb.base/range-stepping.exp: Likewise.
* gdb.cp/annota2.exp: Likewise.
* gdb.cp/annota3.exp: Likewise.
* gdb.gdb/selftest.exp: Likewise.
* gdb.threads/continue-pending-status.exp: Likewise.
* gdb.threads/leader-exit.exp: Likewise.
* gdb.threads/manythreads.exp: Likewise.
* gdb.threads/pthreads.exp: Likewise.
* gdb.threads/schedlock.exp: Likewise.
* gdb.threads/sigthread.exp: Likewise.

Target remote mode fork and exec event documentation

This patch implements documentation updates for target remote mode fork and
exec events. A summary of the rationale for the changes made here:

* Connecting to a remote target -- explain that the two protocols exist.

* Connecting in target remote mode -- explain invoking gdbserver for target
remote mode, and move remote-specific text from original "Connecting to a
remote target" section.

* Connecting in target extended-remote mode -- promote this section from
"Using the gdbserver Program | Running gdbserver | Multi-Process Mode for
gdbserver". Put it next to the target remote mode section.

* Host and target files -- collect paragraphs dealing with how to locate
symbol files from original sections "Connecting to a remote target" and
"Using the gdbserver program | Connecting to gdbserver".

* Steps for connecting to a remote target -- used to be "Using the
gdbserver program | Connecting to gdbserver"

* Remote connection commands -- used to be the bulk of "Connecting to a
remote target". Added "target extended-remote" commands and information.

gdb/ChangeLog:

* NEWS: Announce fork and exec event support for target remote.

gdb/doc/ChangeLog:

* gdb.texinfo (Forks): Correct Linux kernel version where
fork and exec events are supported, add notes about support
of these events in target remote mode.
(Connecting): Reorganize and clarify distinctions between
target remote, extended-remote, and multiprocess.
Reorganize related text from separate sections into new
sections.
(Server): Note effects of target extended-remote mode.
Delete section on Multi-Process Mode for gdbserver.
Move some text to "Connecting" node.

Target remote mode fork and exec event support

This patch implements support for fork and exec events with target remote
mode Linux targets. For such targets with Linux kernels 2.5.46 and later,
this enables follow-fork-mode, detach-on-fork and fork and exec
catchpoints.

The changes required to implement this included:

* Don't exit from gdbserver if there are still active inferiors.

* Allow changing the active process in remote mode.

* Enable fork and exec events in remote mode.

* Print "Ending remote debugging" only when disconnecting.

* Combine remote_kill and extended_remote_kill into a single function
that can handle the multiple inferior case for target remote. Also,
the same thing for remote_mourn and extended_remote_mourn.

* Enable process-style ptids in target remote.

* Remove restriction on multiprocess mode in target remote.

gdb/gdbserver/ChangeLog:

* server.c (process_serial_event): Don't exit from gdbserver
in remote mode if there are still active inferiors.

gdb/ChangeLog:

* inferior.c (number_of_live_inferiors): New function.
(have_live_inferiors): Use number_of_live_inferiors in place
of duplicate code.
* inferior.h (number_of_live_inferiors): Declare new function.
* remote.c (set_general_process): Remove restriction on target
remote mode.
(remote_query_supported): Likewise.
(remote_detach_1): Exit in target remote mode only when there
is just one live inferior left.
(remote_disconnect): Unpush the target directly instead of
calling remote_mourn.
(remote_kill): Rewrite function to handle both target remote
and extended-remote. Call remote_kill_k.
(remote_kill_k): New function.
(extended_remote_kill): Delete function.
(remote_mourn, extended_remote_mourn): Combine functions into
one, remote_mourn, and enable extended functionality for target
remote.
(remote_pid_to_str): Enable "process" style ptid string for
target remote.
(remote_supports_multi_process): Remove restriction on target
remote mode.

Target remote mode fork and exec test updates

This patch updates tests for fork and exec events in target remote mode.
In the majority of cases this was a simple matter of removing some code
that disabled the test for target remote. In a few cases the test needed
to be disabled; in those cases the gdb_protocol was checked instead of
using the [is_remote target] etc.

In a couple of cases we needed to use clean_restart, since target remote
doesn't support the run command, and in one case we had to modify an expect
expression to allow for a "multiprocess-style" ptid.

Tested with the patch that implemented target remote mode fork and exec
event support.

gdb/testsuite/ChangeLog:

* gdb.base/execl-update-breakpoints.exp (main): Enable for target
remote.
* gdb.base/foll-exec-mode.exp (main): Disable for target remote.
* gdb.base/foll-exec.exp (main): Enable for target remote.
* gdb.base/foll-fork.exp (main): Likewise.
* gdb.base/foll-vfork.exp (main): Likewise.
* gdb.base/multi-forks.exp (main): Likewise, and use clean_restart.
(proc continue_to_exit_bp_loc): Use clean_restart.
* gdb.base/pie-execl.exp (main): Disable for target remote.
* gdb.base/watch-vfork.exp (main): Enable for target remote.
* gdb.mi/mi-nsthrexec.exp (main): Likewise.
* gdb.threads/execl.exp (main): Likewise.
* gdb.threads/fork-child-threads.exp (main): Likewise.
* gdb.threads/fork-plus-threads.exp (main): Disable for target
remote.
* gdb.threads/fork-thread-pending.exp (main): Enable for target
remote.
* gdb.threads/linux-dp.exp (check_philosopher_stack): Allow
pid.tid style ptids, instead of just tid.
* gdb.threads/thread-execl.exp (main): Enable for target remote.
* gdb.threads/watchpoint-fork.exp (main): Likewise.
* gdb.trace/report.exp (use_collected_data): Allow pid.tid style
ptids, instead of just tid.

[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
<OP> <Hd>, <Hs>, #<imm>

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.

Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff

[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.

The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, #<imm>
where T is 4h or 8h.

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
specifier.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_VSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD shift by immediate group.

Change-Id: I3480f63883d54db46562573185da6982f2365ee8

[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.

The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP

The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
Pairwise instructions.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_PAIR_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.

Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345

[AArch64][PATCH 11/14] Add support for the 2H vector type.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.

The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.

gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
take into account new vector type 2H.
(vectype_to_qualifier): Likewise.

include/opcode/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64.h (enum aarch64_opnd_qualifier): Add
AARCH64_OPND_QLF_V_2H.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>

* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
and adjust calculation to ignore qualifier for type 2H.
* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".

Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126

[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type. This patch reworks
code in the assembler to allow the addition of the new type.

The new vector type requires the addtion of a new operand qualifier to
the enum aarch64_opnd_qualifier which is defined
include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_.

The correctness of the GAS utility function
tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and
ordering of this group. In particular, it makes assumptions about the
positions of the members of the group that are not true if a qualifier
for type 2H is added before the qualifier for 4H.

This patch reworks the function to weaken its assumptions, making it
calculate positions in the group from the type (B, H, S, D, Q) and
register width.

gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
qualifier from per-type base and offet.

Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1

[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.

The instruction added is: FMOV.

The form of this instructions is
<OP> <Hd>, #<imm>

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
instructions.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SIMD_IMM_H): New.
(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
modified immediate group.

Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2

[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.

The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.

The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.

The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
specifier.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_XLANES_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
fminnmv, fminv to the Adv.SIMD across lanes group.

Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c

[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.

The instructions added are: FMLA, FMLS, FMUL and FMULX.

The general form for these instructions is
<OP> <Hd>, <Hs>, <V>.h[<idx>]

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
instructions.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
fmls, fmul and fmulx to the scalar indexed element group.

Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627

[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.

The instructions added are: FMLA, FMLS, FMUL and FMULX.

The general form for these instructions is
<OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
where T is 4h or 8h

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
instructions.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
fmulx to the vector indexed element group.

Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4

[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.

The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.

The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.

opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>

* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.

Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c