Commit: 2dc7553d0c0a3915c649e1a91b0f0be70b4674b3 - qemu (git)

Commit MetaInfo

• Revisión: 2dc7553d0c0a3915c649e1a91b0f0be70b4674b3 (tree)
• Tiempo: 2016-04-06 04:47:47
• Autor: James Hogan <james.hogan@imgt...>
• Commiter: Richard Henderson

Log Message

tcg/mips: Fix type of tcg_target_reg_alloc_order[]

The MIPS TCG backend is the only one to have
tcg_target_reg_alloc_order[] elements of type TCGReg rather than int.
This resulted in commit 91478cefaaf2 ("tcg: Allocate indirect_base
temporaries in a different order") breaking the build on MIPS since the
type differed from indirect_reg_alloc_order[]:

tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror]

order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order;

Make it an array of ints to fix the build and match other architectures.

Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different order")
Signed-off-by: James Hogan <[e-mail]>
Acked-by: Aurelien Jarno <[e-mail]>
Message-Id: <[e-mail]>
Signed-off-by: Richard Henderson <[e-mail]>

Cambiar Resumen

• modified: tcg/mips/tcg-target.inc.c

Diferencia incremental

--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -76,7 +76,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 #define TCG_TMP1  TCG_REG_T9
 
 /* check if we really need so many registers :P */
-static const TCGReg tcg_target_reg_alloc_order[] = {
+static const int tcg_target_reg_alloc_order[] = {
     /* Call saved registers.  */
     TCG_REG_S0,
     TCG_REG_S1,