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Revisión6ad4d7eed05a1e23537fc92b50f898f5977f37e6 (tree)
Tiempo2017-09-08 03:15:55
AutorPeter Maydell <peter.maydell@lina...>
CommiterRichard Henderson

Log Message

target/alpha: Switch to do_transaction_failed() hook

Switch the alpha target from the old unassigned_access hook
to the new do_transaction_failed hook. This allows us to
resolve a ??? in the old hook implementation.

The only part of the alpha target that does physical
memory accesses is reading the page table -- add a
TODO comment there to the effect that we should handle
bus faults on page table walks. (Since the palcode
doesn't actually do anything useful on a bus fault anyway
it's a bit moot for now.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <1502196172-13818-1-git-send-email-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Cambiar Resumen

Diferencia incremental

--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -297,7 +297,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
297297 #ifdef CONFIG_USER_ONLY
298298 cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
299299 #else
300- cc->do_unassigned_access = alpha_cpu_unassigned_access;
300+ cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
301301 cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
302302 cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
303303 dc->vmsd = &vmstate_alpha_cpu;
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -486,9 +486,11 @@ void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
486486 uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
487487 void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
488488 #ifndef CONFIG_USER_ONLY
489-QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
490- bool is_write, bool is_exec,
491- int unused, unsigned size);
489+void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
490+ vaddr addr, unsigned size,
491+ MMUAccessType access_type,
492+ int mmu_idx, MemTxAttrs attrs,
493+ MemTxResult response, uintptr_t retaddr);
492494 #endif
493495
494496 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -163,6 +163,14 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr,
163163
164164 pt = env->ptbr;
165165
166+ /* TODO: rather than using ldq_phys() to read the page table we should
167+ * use address_space_ldq() so that we can handle the case when
168+ * the page table read gives a bus fault, rather than ignoring it.
169+ * For the existing code the zero data that ldq_phys will return for
170+ * an access to invalid memory will result in our treating the page
171+ * table as invalid, which may even be the right behaviour.
172+ */
173+
166174 /* L1 page table read. */
167175 index = (addr >> (TARGET_PAGE_BITS + 20)) & 0x3ff;
168176 L1pte = ldq_phys(cs->as, pt + index*8);
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -49,22 +49,23 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
4949 cpu_loop_exit(cs);
5050 }
5151
52-void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
53- bool is_write, bool is_exec, int unused,
54- unsigned size)
52+void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
53+ vaddr addr, unsigned size,
54+ MMUAccessType access_type,
55+ int mmu_idx, MemTxAttrs attrs,
56+ MemTxResult response, uintptr_t retaddr)
5557 {
5658 AlphaCPU *cpu = ALPHA_CPU(cs);
5759 CPUAlphaState *env = &cpu->env;
5860
61+ if (retaddr) {
62+ cpu_restore_state(cs, retaddr);
63+ }
64+
5965 env->trap_arg0 = addr;
60- env->trap_arg1 = is_write ? 1 : 0;
66+ env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0;
6167 cs->exception_index = EXCP_MCHK;
6268 env->error_code = 0;
63-
64- /* ??? We should cpu_restore_state to the faulting insn, but this hook
65- does not have access to the retaddr value from the original helper.
66- It's all moot until the QEMU PALcode grows an MCHK handler. */
67-
6869 cpu_loop_exit(cs);
6970 }
7071