Revisión | 3a6cf2ded716122313e90436b0d9afaebae4e70d (tree) |
---|---|
Tiempo | 2022-07-14 06:03:37 |
Autor | Weijie Gao <weijie.gao@medi...> |
Commiter | Daniel Schwierzeck |
mips: add more definitions for asm/cm.h
This patch add more definitions needed for MT7621 initialization.
MT7621 needs to initialize GIC/CPC and other related parts.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
@@ -8,9 +8,23 @@ | ||
8 | 8 | #define __MIPS_ASM_CM_H__ |
9 | 9 | |
10 | 10 | /* Global Control Register (GCR) offsets */ |
11 | +#define GCR_CONFIG 0x0000 | |
11 | 12 | #define GCR_BASE 0x0008 |
12 | 13 | #define GCR_BASE_UPPER 0x000c |
14 | +#define GCR_CONTROL 0x0010 | |
15 | +#define GCR_ACCESS 0x0020 | |
13 | 16 | #define GCR_REV 0x0030 |
17 | +#define GCR_GIC_BASE 0x0080 | |
18 | +#define GCR_CPC_BASE 0x0088 | |
19 | +#define GCR_REG0_BASE 0x0090 | |
20 | +#define GCR_REG0_MASK 0x0098 | |
21 | +#define GCR_REG1_BASE 0x00a0 | |
22 | +#define GCR_REG1_MASK 0x00a8 | |
23 | +#define GCR_REG2_BASE 0x00b0 | |
24 | +#define GCR_REG2_MASK 0x00b8 | |
25 | +#define GCR_REG3_BASE 0x00c0 | |
26 | +#define GCR_REG3_MASK 0x00c8 | |
27 | +#define GCR_CPC_STATUS 0x00f0 | |
14 | 28 | #define GCR_L2_CONFIG 0x0130 |
15 | 29 | #define GCR_L2_TAG_ADDR 0x0600 |
16 | 30 | #define GCR_L2_TAG_ADDR_UPPER 0x0604 |
@@ -19,10 +33,59 @@ | ||
19 | 33 | #define GCR_L2_DATA 0x0610 |
20 | 34 | #define GCR_L2_DATA_UPPER 0x0614 |
21 | 35 | #define GCR_Cx_COHERENCE 0x2008 |
36 | +#define GCR_Cx_OTHER 0x2018 | |
37 | +#define GCR_Cx_ID 0x2028 | |
38 | +#define GCR_CO_COHERENCE 0x4008 | |
39 | + | |
40 | +/* GCR_CONFIG fields */ | |
41 | +#define GCR_CONFIG_NUM_CLUSTERS_SHIFT 23 | |
42 | +#define GCR_CONFIG_NUM_CLUSTERS (0x7f << 23) | |
43 | +#define GCR_CONFIG_NUMIOCU_SHIFT 8 | |
44 | +#define GCR_CONFIG_NUMIOCU (0xff << 8) | |
45 | +#define GCR_CONFIG_PCORES_SHIFT 0 | |
46 | +#define GCR_CONFIG_PCORES (0xff << 0) | |
47 | + | |
48 | +/* GCR_BASE fields */ | |
49 | +#define GCR_BASE_SHIFT 15 | |
50 | +#define CCA_DEFAULT_OVR_SHIFT 5 | |
51 | +#define CCA_DEFAULT_OVR_MASK (0x7 << 5) | |
52 | +#define CCA_DEFAULT_OVREN (0x1 << 4) | |
53 | +#define CM_DEFAULT_TARGET_SHIFT 0 | |
54 | +#define CM_DEFAULT_TARGET_MASK (0x3 << 0) | |
55 | + | |
56 | +/* GCR_CONTROL fields */ | |
57 | +#define GCR_CONTROL_SYNCCTL (0x1 << 16) | |
22 | 58 | |
23 | 59 | /* GCR_REV CM versions */ |
24 | 60 | #define GCR_REV_CM3 0x0800 |
25 | 61 | |
62 | +/* GCR_GIC_BASE fields */ | |
63 | +#define GCR_GIC_BASE_ADDRMASK_SHIFT 7 | |
64 | +#define GCR_GIC_BASE_ADDRMASK (0x1ffffff << 7) | |
65 | +#define GCR_GIC_EN (0x1 << 0) | |
66 | + | |
67 | +/* GCR_CPC_BASE fields */ | |
68 | +#define GCR_CPC_BASE_ADDRMASK_SHIFT 15 | |
69 | +#define GCR_CPC_BASE_ADDRMASK (0x1ffff << 15) | |
70 | +#define GCR_CPC_EN (0x1 << 0) | |
71 | + | |
72 | +/* GCR_REGn_MASK fields */ | |
73 | +#define GCR_REGn_MASK_ADDRMASK_SHIFT 16 | |
74 | +#define GCR_REGn_MASK_ADDRMASK (0xffff << 16) | |
75 | +#define GCR_REGn_MASK_CCAOVR_SHIFT 5 | |
76 | +#define GCR_REGn_MASK_CCAOVR (0x7 << 5) | |
77 | +#define GCR_REGn_MASK_CCAOVREN (1 << 4) | |
78 | +#define GCR_REGn_MASK_DROPL2 (1 << 2) | |
79 | +#define GCR_REGn_MASK_CMTGT_SHIFT 0 | |
80 | +#define GCR_REGn_MASK_CMTGT (0x3 << 0) | |
81 | +#define GCR_REGn_MASK_CMTGT_DISABLED 0x0 | |
82 | +#define GCR_REGn_MASK_CMTGT_MEM 0x1 | |
83 | +#define GCR_REGn_MASK_CMTGT_IOCU0 0x2 | |
84 | +#define GCR_REGn_MASK_CMTGT_IOCU1 0x3 | |
85 | + | |
86 | +/* GCR_CPC_STATUS fields */ | |
87 | +#define GCR_CPC_EX (0x1 << 0) | |
88 | + | |
26 | 89 | /* GCR_L2_CONFIG fields */ |
27 | 90 | #define GCR_L2_CONFIG_ASSOC_SHIFT 0 |
28 | 91 | #define GCR_L2_CONFIG_ASSOC_BITS 8 |
@@ -36,6 +99,10 @@ | ||
36 | 99 | #define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) |
37 | 100 | #define GCR_Cx_COHERENCE_EN (0x1 << 0) |
38 | 101 | |
102 | +/* GCR_Cx_OTHER fields */ | |
103 | +#define GCR_Cx_OTHER_CORENUM_SHIFT 16 | |
104 | +#define GCR_Cx_OTHER_CORENUM (0xffff << 16) | |
105 | + | |
39 | 106 | #ifndef __ASSEMBLY__ |
40 | 107 | |
41 | 108 | #include <asm/io.h> |