| Revisión | 65f146e9ef1f03d786fed51031c84cd4d572c350 (tree) |
|---|---|
| Tiempo | 2016-04-17 18:04:08 |
| Autor | Yoshinori Sato <ysato@user...> |
| Commiter | Yoshinori Sato |
Add SH7206 support.
arch/sh/include/asm/cpu_sh2.h (diff) arch/sh/include/asm/cpu_sh7206.h (diff)| @@ -13,6 +13,8 @@ | ||
| 13 | 13 | #endif |
| 14 | 14 | #if defined(CONFIG_CPU_SH7203) |
| 15 | 15 | # include <asm/cpu_sh7203.h> |
| 16 | +#elif defined(CONFIG_CPU_SH7206) | |
| 17 | +# include <asm/cpu_sh7206.h> | |
| 16 | 18 | #elif defined(CONFIG_CPU_SH7264) |
| 17 | 19 | # include <asm/cpu_sh7264.h> |
| 18 | 20 | #elif defined(CONFIG_CPU_SH7269) |
| @@ -0,0 +1,75 @@ | ||
| 1 | +#ifndef _ASM_CPU_SH7206_H_ | |
| 2 | +#define _ASM_CPU_SH7206_H_ | |
| 3 | + | |
| 4 | +/* Cache */ | |
| 5 | +#define CCR1 0xFFFC1000 | |
| 6 | +#define CCR2 0xFFFC1004 | |
| 7 | +#define CCR CCR1 | |
| 8 | + | |
| 9 | +#define CMNCR 0xFFFC0000 | |
| 10 | +#define CS0BCR 0xFFFC0004 | |
| 11 | +#define CS2BCR 0xFFFC000C | |
| 12 | +#define CS3BCR 0xFFFC0010 | |
| 13 | +#define CS4BCR 0xFFFC0014 | |
| 14 | +#define CS5BCR 0xFFFC0018 | |
| 15 | +#define CS0WCR 0xFFFC0028 | |
| 16 | +#define CS2WCR 0xFFFC0030 | |
| 17 | +#define CS3WCR 0xFFFC0034 | |
| 18 | +#define CS4WCR 0xFFFC0038 | |
| 19 | +#define CS5WCR 0xFFFC003C | |
| 20 | +#define SDCR 0xFFFC004C | |
| 21 | +#define RTCSR 0xFFFC0050 | |
| 22 | +#define RTCNT 0xFFFC0054 | |
| 23 | +#define RTCOR 0xFFFC0058 | |
| 24 | + | |
| 25 | +/* SCIF */ | |
| 26 | +#define SCSMR_0 0xFFFE8000 | |
| 27 | +#define SCSMR_1 0xFFFE8800 | |
| 28 | +#define SCSMR_2 0xFFFE9000 | |
| 29 | +#define SCSMR_3 0xFFFE9800 | |
| 30 | +#define SCIF0_BASE SCSMR_0 | |
| 31 | +#define SCIF1_BASE SCSMR_1 | |
| 32 | +#define SCIF2_BASE SCSMR_2 | |
| 33 | +#define SCIF3_BASE SCSMR_3 | |
| 34 | + | |
| 35 | +/* Timer(CMT) */ | |
| 36 | +#define CMSTR 0xFFFEC000 | |
| 37 | +#define CMCSR_0 0xFFFEC002 | |
| 38 | +#define CMCNT_0 0xFFFEC004 | |
| 39 | +#define CMCOR_0 0xFFFEC006 | |
| 40 | +#define CMCSR_1 0xFFFEC008 | |
| 41 | +#define CMCNT_1 0xFFFEC00A | |
| 42 | +#define CMCOR_1 0xFFFEC00C | |
| 43 | + | |
| 44 | +/* PFC */ | |
| 45 | +#define PACRH3 0xFFFE380A | |
| 46 | +#define PACRH2 0xFFFE380C | |
| 47 | +#define PACRH1 0xFFFE380E | |
| 48 | +#define PACRL4 0xFFFE3810 | |
| 49 | +#define PACRL3 0xFFFE3812 | |
| 50 | +#define PACRL2 0xFFFE3814 | |
| 51 | +#define PACRL1 0xFFFE3816 | |
| 52 | +#define PBCR3 0xFFFE3892 | |
| 53 | +#define PBCR2 0xFFFE3894 | |
| 54 | +#define PBCR1 0xFFFE3896 | |
| 55 | +#define PCCRL1 0xFFFE3916 | |
| 56 | +#define PDCRH4 0xFFFE3988 | |
| 57 | +#define PDCRH3 0xFFFE398A | |
| 58 | +#define PDCRH2 0xFFFE398C | |
| 59 | +#define PDCRH1 0xFFFE398E | |
| 60 | +#define PDCRL4 0xFFFE3990 | |
| 61 | +#define PDCRL3 0xFFFE3992 | |
| 62 | +#define PECRH1 0xFFFE3A0E | |
| 63 | +#define PECRL4 0xFFFE3A10 | |
| 64 | +#define PECRL3 0xFFFE3A12 | |
| 65 | +#define PECRL2 0xFFFE3A14 | |
| 66 | +#define IFCR 0xFFFE3A22 | |
| 67 | + | |
| 68 | +/* On chip oscillator circuits */ | |
| 69 | +#define FRQCR 0xFFFE0010 | |
| 70 | +#define MCLKCR 0xFFFE0410 | |
| 71 | +/* Watchdog timer */ | |
| 72 | +#define WTCNT 0xFFFE0002 | |
| 73 | +#define WTCSR 0xFFFE0000 | |
| 74 | + | |
| 75 | +#endif /* _ASM_CPU_SH7206_H_ */ |
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