Revisión | 896e2ca9125480d5c433cbdf4d06d7a5bcd6a3b1 (tree) |
---|---|
Tiempo | 2011-02-21 16:30:55 |
Autor | Lei Wen <[leiwen@marv...> |
Commiter | Albert Aribaud |
ARM: Add Support for Marvell Pantheon Familiy SoCs
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
SoC versions Supported:
1) PANTHEON920 (TD)
2) PANTHEON910 (TTC)
Signed-off-by: Lei Wen <leiwen@marvell.com>
@@ -0,0 +1,46 @@ | ||
1 | +# | |
2 | +# (C) Copyright 2011 | |
3 | +# Marvell Semiconductor <www.marvell.com> | |
4 | +# Written-by: Lei Wen <leiwen@marvell.com> | |
5 | +# | |
6 | +# See file CREDITS for list of people who contributed to this | |
7 | +# project. | |
8 | +# | |
9 | +# This program is free software; you can redistribute it and/or | |
10 | +# modify it under the terms of the GNU General Public License as | |
11 | +# published by the Free Software Foundation; either version 2 of | |
12 | +# the License, or (at your option) any later version. | |
13 | +# | |
14 | +# This program is distributed in the hope that it will be useful, | |
15 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | +# GNU General Public License for more details. | |
18 | +# | |
19 | +# You should have received a copy of the GNU General Public License | |
20 | +# along with this program; if not, write to the Free Software | |
21 | +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
22 | +# MA 02110-1301 USA | |
23 | +# | |
24 | + | |
25 | +include $(TOPDIR)/config.mk | |
26 | + | |
27 | +LIB = $(obj)lib$(SOC).o | |
28 | + | |
29 | +COBJS-y = cpu.o timer.o dram.o | |
30 | + | |
31 | +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) | |
32 | +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) | |
33 | + | |
34 | +all: $(obj).depend $(LIB) | |
35 | + | |
36 | +$(LIB): $(OBJS) | |
37 | + $(AR) $(ARFLAGS) $@ $(OBJS) | |
38 | + | |
39 | +######################################################################### | |
40 | + | |
41 | +# defines $(obj).depend target | |
42 | +include $(SRCTREE)/rules.mk | |
43 | + | |
44 | +sinclude $(obj).depend | |
45 | + | |
46 | +######################################################################### |
@@ -0,0 +1,78 @@ | ||
1 | +/* | |
2 | + * (C) Copyright 2011 | |
3 | + * Marvell Semiconductor <www.marvell.com> | |
4 | + * Written-by: Lei Wen <leiwen@marvell.com> | |
5 | + * | |
6 | + * See file CREDITS for list of people who contributed to this | |
7 | + * project. | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or | |
10 | + * modify it under the terms of the GNU General Public License as | |
11 | + * published by the Free Software Foundation; either version 2 of | |
12 | + * the License, or (at your option) any later version. | |
13 | + * | |
14 | + * This program is distributed in the hope that it will be useful, | |
15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | + * GNU General Public License for more details. | |
18 | + * | |
19 | + * You should have received a copy of the GNU General Public License | |
20 | + * along with this program; if not, write to the Free Software | |
21 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
22 | + * MA 02110-1301 USA | |
23 | + */ | |
24 | + | |
25 | +#include <common.h> | |
26 | +#include <asm/arch/pantheon.h> | |
27 | +#include <asm/io.h> | |
28 | + | |
29 | +#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) | |
30 | +#define SET_MRVL_ID (1<<8) | |
31 | +#define L2C_RAM_SEL (1<<4) | |
32 | + | |
33 | +int arch_cpu_init(void) | |
34 | +{ | |
35 | + u32 val; | |
36 | + struct panthcpu_registers *cpuregs = | |
37 | + (struct panthcpu_registers*) PANTHEON_CPU_BASE; | |
38 | + | |
39 | + struct panthapb_registers *apbclkres = | |
40 | + (struct panthapb_registers*) PANTHEON_APBC_BASE; | |
41 | + | |
42 | + struct panthmpmu_registers *mpmu = | |
43 | + (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; | |
44 | + | |
45 | + /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ | |
46 | + val = readl(&cpuregs->cpu_conf); | |
47 | + val = val | SET_MRVL_ID; | |
48 | + writel(val, &cpuregs->cpu_conf); | |
49 | + | |
50 | + /* Turn on clock gating (PMUM_CCGR) */ | |
51 | + writel(0xFFFFFFFF, &mpmu->ccgr); | |
52 | + | |
53 | + /* Turn on clock gating (PMUM_ACGR) */ | |
54 | + writel(0xFFFFFFFF, &mpmu->acgr); | |
55 | + | |
56 | + /* Turn on uart2 clock */ | |
57 | + writel(UARTCLK14745KHZ, &apbclkres->uart0); | |
58 | + | |
59 | + /* Enable GPIO clock */ | |
60 | + writel(APBC_APBCLK, &apbclkres->gpio); | |
61 | + | |
62 | + icache_enable(); | |
63 | + | |
64 | + return 0; | |
65 | +} | |
66 | + | |
67 | +#if defined(CONFIG_DISPLAY_CPUINFO) | |
68 | +int print_cpuinfo(void) | |
69 | +{ | |
70 | + u32 id; | |
71 | + struct panthcpu_registers *cpuregs = | |
72 | + (struct panthcpu_registers*) PANTHEON_CPU_BASE; | |
73 | + | |
74 | + id = readl(&cpuregs->chip_id); | |
75 | + printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); | |
76 | + return 0; | |
77 | +} | |
78 | +#endif |
@@ -0,0 +1,132 @@ | ||
1 | +/* | |
2 | + * (C) Copyright 2011 | |
3 | + * Marvell Semiconductor <www.marvell.com> | |
4 | + * Written-by: Lei Wen <leiwen@marvell.com>, | |
5 | + * | |
6 | + * See file CREDITS for list of people who contributed to this | |
7 | + * project. | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or | |
10 | + * modify it under the terms of the GNU General Public License as | |
11 | + * published by the Free Software Foundation; either version 2 of | |
12 | + * the License, or (at your option) any later version. | |
13 | + * | |
14 | + * This program is distributed in the hope that it will be useful, | |
15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | + * GNU General Public License for more details. | |
18 | + * | |
19 | + * You should have received a copy of the GNU General Public License | |
20 | + * along with this program; if not, write to the Free Software | |
21 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
22 | + * MA 02110-1301 USA | |
23 | + */ | |
24 | + | |
25 | +#include <common.h> | |
26 | +#include <asm/arch/pantheon.h> | |
27 | + | |
28 | +DECLARE_GLOBAL_DATA_PTR; | |
29 | + | |
30 | +/* | |
31 | + * Pantheon DRAM controller supports upto 8 banks | |
32 | + * for chip select 0 and 1 | |
33 | + */ | |
34 | + | |
35 | +/* | |
36 | + * DDR Memory Control Registers | |
37 | + * Refer Datasheet 4.4 | |
38 | + */ | |
39 | +struct panthddr_map_registers { | |
40 | + u32 cs; /* Memory Address Map Register -CS */ | |
41 | + u32 pad[3]; | |
42 | +}; | |
43 | + | |
44 | +struct panthddr_registers { | |
45 | + u8 pad[0x100 - 0x000]; | |
46 | + struct panthddr_map_registers mmap[2]; | |
47 | +}; | |
48 | + | |
49 | +/* | |
50 | + * panth_sdram_base - reads SDRAM Base Address Register | |
51 | + */ | |
52 | +u32 panth_sdram_base(int chip_sel) | |
53 | +{ | |
54 | + struct panthddr_registers *ddr_regs = | |
55 | + (struct panthddr_registers *)PANTHEON_DRAM_BASE; | |
56 | + u32 result = 0; | |
57 | + u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); | |
58 | + | |
59 | + if (!CS_valid) | |
60 | + return 0; | |
61 | + | |
62 | + result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; | |
63 | + return result; | |
64 | +} | |
65 | + | |
66 | +/* | |
67 | + * panth_sdram_size - reads SDRAM size | |
68 | + */ | |
69 | +u32 panth_sdram_size(int chip_sel) | |
70 | +{ | |
71 | + struct panthddr_registers *ddr_regs = | |
72 | + (struct panthddr_registers *)PANTHEON_DRAM_BASE; | |
73 | + u32 result = 0; | |
74 | + u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); | |
75 | + | |
76 | + if (!CS_valid) | |
77 | + return 0; | |
78 | + | |
79 | + result = readl(&ddr_regs->mmap[chip_sel].cs); | |
80 | + result = (result >> 16) & 0xF; | |
81 | + if (result < 0x7) { | |
82 | + printf("Unknown DRAM Size\n"); | |
83 | + return -1; | |
84 | + } else { | |
85 | + return ((0x8 << (result - 0x7)) * 1024 * 1024); | |
86 | + } | |
87 | +} | |
88 | + | |
89 | +#ifndef CONFIG_SYS_BOARD_DRAM_INIT | |
90 | +int dram_init(void) | |
91 | +{ | |
92 | + int i; | |
93 | + | |
94 | + gd->ram_size = 0; | |
95 | + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
96 | + gd->bd->bi_dram[i].start = panth_sdram_base(i); | |
97 | + gd->bd->bi_dram[i].size = panth_sdram_size(i); | |
98 | + /* | |
99 | + * It is assumed that all memory banks are consecutive | |
100 | + * and without gaps. | |
101 | + * If the gap is found, ram_size will be reported for | |
102 | + * consecutive memory only | |
103 | + */ | |
104 | + if (gd->bd->bi_dram[i].start != gd->ram_size) | |
105 | + break; | |
106 | + | |
107 | + gd->ram_size += gd->bd->bi_dram[i].size; | |
108 | + | |
109 | + } | |
110 | + | |
111 | + for (; i < CONFIG_NR_DRAM_BANKS; i++) { | |
112 | + /* | |
113 | + * If above loop terminated prematurely, we need to set | |
114 | + * remaining banks' start address & size as 0. Otherwise other | |
115 | + * u-boot functions and Linux kernel gets wrong values which | |
116 | + * could result in crash | |
117 | + */ | |
118 | + gd->bd->bi_dram[i].start = 0; | |
119 | + gd->bd->bi_dram[i].size = 0; | |
120 | + } | |
121 | + return 0; | |
122 | +} | |
123 | + | |
124 | +/* | |
125 | + * If this function is not defined here, | |
126 | + * board.c alters dram bank zero configuration defined above. | |
127 | + */ | |
128 | +void dram_init_banksize(void) | |
129 | +{ | |
130 | + dram_init(); | |
131 | +} | |
132 | +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ |
@@ -0,0 +1,214 @@ | ||
1 | +/* | |
2 | + * (C) Copyright 2011 | |
3 | + * Marvell Semiconductor <www.marvell.com> | |
4 | + * Written-by: Lei Wen <leiwen@marvell.com> | |
5 | + * | |
6 | + * See file CREDITS for list of people who contributed to this | |
7 | + * project. | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or | |
10 | + * modify it under the terms of the GNU General Public License as | |
11 | + * published by the Free Software Foundation; either version 2 of | |
12 | + * the License, or (at your option) any later version. | |
13 | + * | |
14 | + * This program is distributed in the hope that it will be useful, | |
15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | + * GNU General Public License for more details. | |
18 | + * | |
19 | + * You should have received a copy of the GNU General Public License | |
20 | + * along with this program; if not, write to the Free Software | |
21 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
22 | + * MA 02110-1301 USA | |
23 | + */ | |
24 | + | |
25 | +#include <common.h> | |
26 | +#include <asm/arch/pantheon.h> | |
27 | + | |
28 | +/* | |
29 | + * Timer registers | |
30 | + * Refer 6.2.9 in Datasheet | |
31 | + */ | |
32 | +struct panthtmr_registers { | |
33 | + u32 clk_ctrl; /* Timer clk control reg */ | |
34 | + u32 match[9]; /* Timer match registers */ | |
35 | + u32 count[3]; /* Timer count registers */ | |
36 | + u32 status[3]; | |
37 | + u32 ie[3]; | |
38 | + u32 preload[3]; /* Timer preload value */ | |
39 | + u32 preload_ctrl[3]; | |
40 | + u32 wdt_match_en; | |
41 | + u32 wdt_match_r; | |
42 | + u32 wdt_val; | |
43 | + u32 wdt_sts; | |
44 | + u32 icr[3]; | |
45 | + u32 wdt_icr; | |
46 | + u32 cer; /* Timer count enable reg */ | |
47 | + u32 cmr; | |
48 | + u32 ilr[3]; | |
49 | + u32 wcr; | |
50 | + u32 wfar; | |
51 | + u32 wsar; | |
52 | + u32 cvwr[3]; | |
53 | +}; | |
54 | + | |
55 | +#define TIMER 0 /* Use TIMER 0 */ | |
56 | +/* Each timer has 3 match registers */ | |
57 | +#define MATCH_CMP(x) ((3 * TIMER) + x) | |
58 | +#define TIMER_LOAD_VAL 0xffffffff | |
59 | +#define COUNT_RD_REQ 0x1 | |
60 | + | |
61 | +DECLARE_GLOBAL_DATA_PTR; | |
62 | +/* Using gd->tbu from timestamp and gd->tbl for lastdec */ | |
63 | + | |
64 | +/* | |
65 | + * For preventing risk of instability in reading counter value, | |
66 | + * first set read request to register cvwr and then read same | |
67 | + * register after it captures counter value. | |
68 | + */ | |
69 | +ulong read_timer(void) | |
70 | +{ | |
71 | + struct panthtmr_registers *panthtimers = | |
72 | + (struct panthtmr_registers *) PANTHEON_TIMER_BASE; | |
73 | + volatile int loop=100; | |
74 | + ulong val; | |
75 | + | |
76 | + writel(COUNT_RD_REQ, &panthtimers->cvwr); | |
77 | + while (loop--) | |
78 | + val = readl(&panthtimers->cvwr); | |
79 | + | |
80 | + /* | |
81 | + * This stop gcc complain and prevent loop mistake init to 0 | |
82 | + */ | |
83 | + val = readl(&panthtimers->cvwr); | |
84 | + | |
85 | + return val; | |
86 | +} | |
87 | + | |
88 | +void reset_timer_masked(void) | |
89 | +{ | |
90 | + /* reset time */ | |
91 | + gd->tbl = read_timer(); | |
92 | + gd->tbu = 0; | |
93 | +} | |
94 | + | |
95 | +ulong get_timer_masked(void) | |
96 | +{ | |
97 | + ulong now = read_timer(); | |
98 | + | |
99 | + if (now >= gd->tbl) { | |
100 | + /* normal mode */ | |
101 | + gd->tbu += now - gd->tbl; | |
102 | + } else { | |
103 | + /* we have an overflow ... */ | |
104 | + gd->tbu += now + TIMER_LOAD_VAL - gd->tbl; | |
105 | + } | |
106 | + gd->tbl = now; | |
107 | + | |
108 | + return gd->tbu; | |
109 | +} | |
110 | + | |
111 | +void reset_timer(void) | |
112 | +{ | |
113 | + reset_timer_masked(); | |
114 | +} | |
115 | + | |
116 | +ulong get_timer(ulong base) | |
117 | +{ | |
118 | + return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - | |
119 | + base); | |
120 | +} | |
121 | + | |
122 | +void set_timer(ulong t) | |
123 | +{ | |
124 | + gd->tbu = t; | |
125 | +} | |
126 | + | |
127 | +void __udelay(unsigned long usec) | |
128 | +{ | |
129 | + ulong delayticks; | |
130 | + ulong endtime; | |
131 | + | |
132 | + delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); | |
133 | + endtime = get_timer_masked() + delayticks; | |
134 | + | |
135 | + while (get_timer_masked() < endtime) | |
136 | + ; | |
137 | +} | |
138 | + | |
139 | +/* | |
140 | + * init the Timer | |
141 | + */ | |
142 | +int timer_init(void) | |
143 | +{ | |
144 | + struct panthapb_registers *apb1clkres = | |
145 | + (struct panthapb_registers *) PANTHEON_APBC_BASE; | |
146 | + struct panthtmr_registers *panthtimers = | |
147 | + (struct panthtmr_registers *) PANTHEON_TIMER_BASE; | |
148 | + | |
149 | + /* Enable Timer clock at 3.25 MHZ */ | |
150 | + writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); | |
151 | + | |
152 | + /* load value into timer */ | |
153 | + writel(0x0, &panthtimers->clk_ctrl); | |
154 | + /* Use Timer 0 Match Resiger 0 */ | |
155 | + writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]); | |
156 | + /* Preload value is 0 */ | |
157 | + writel(0x0, &panthtimers->preload[TIMER]); | |
158 | + /* Enable match comparator 0 for Timer 0 */ | |
159 | + writel(0x1, &panthtimers->preload_ctrl[TIMER]); | |
160 | + | |
161 | + /* Enable timer 0 */ | |
162 | + writel(0x1, &panthtimers->cer); | |
163 | + /* init the gd->tbu and gd->tbl value */ | |
164 | + reset_timer_masked(); | |
165 | + | |
166 | + return 0; | |
167 | +} | |
168 | + | |
169 | +#define MPMU_APRR_WDTR (1<<4) | |
170 | +#define TMR_WFAR 0xbaba /* WDT Register First key */ | |
171 | +#define TMP_WSAR 0xeb10 /* WDT Register Second key */ | |
172 | + | |
173 | +/* | |
174 | + * This function uses internal Watchdog Timer | |
175 | + * based reset mechanism. | |
176 | + * Steps to write watchdog registers (protected access) | |
177 | + * 1. Write key value to TMR_WFAR reg. | |
178 | + * 2. Write key value to TMP_WSAR reg. | |
179 | + * 3. Perform write operation. | |
180 | + */ | |
181 | +void reset_cpu (unsigned long ignored) | |
182 | +{ | |
183 | + struct panthmpmu_registers *mpmu = | |
184 | + (struct panthmpmu_registers *) PANTHEON_MPMU_BASE; | |
185 | + struct panthtmr_registers *panthtimers = | |
186 | + (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE; | |
187 | + u32 val; | |
188 | + | |
189 | + /* negate hardware reset to the WDT after system reset */ | |
190 | + val = readl(&mpmu->aprr); | |
191 | + val = val | MPMU_APRR_WDTR; | |
192 | + writel(val, &mpmu->aprr); | |
193 | + | |
194 | + /* reset/enable WDT clock */ | |
195 | + writel(APBC_APBCLK, &mpmu->wdtpcr); | |
196 | + | |
197 | + /* clear previous WDT status */ | |
198 | + writel(TMR_WFAR, &panthtimers->wfar); | |
199 | + writel(TMP_WSAR, &panthtimers->wsar); | |
200 | + writel(0, &panthtimers->wdt_sts); | |
201 | + | |
202 | + /* set match counter */ | |
203 | + writel(TMR_WFAR, &panthtimers->wfar); | |
204 | + writel(TMP_WSAR, &panthtimers->wsar); | |
205 | + writel(0xf, &panthtimers->wdt_match_r); | |
206 | + | |
207 | + /* enable WDT reset */ | |
208 | + writel(TMR_WFAR, &panthtimers->wfar); | |
209 | + writel(TMP_WSAR, &panthtimers->wsar); | |
210 | + writel(0x3, &panthtimers->wdt_match_en); | |
211 | + | |
212 | + /*enable functional WDT clock */ | |
213 | + writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); | |
214 | +} |
@@ -0,0 +1,38 @@ | ||
1 | +/* | |
2 | + * (C) Copyright 2011 | |
3 | + * Marvell Semiconductor <www.marvell.com> | |
4 | + * Written-by: Lei Wen <leiwen@marvell.com> | |
5 | + * | |
6 | + * See file CREDITS for list of people who contributed to this | |
7 | + * project. | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or | |
10 | + * modify it under the terms of the GNU General Public License as | |
11 | + * published by the Free Software Foundation; either version 2 of | |
12 | + * the License, or (at your option) any later version. | |
13 | + * | |
14 | + * This program is distributed in the hope that it will be useful, | |
15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | + * GNU General Public License for more details. | |
18 | + * | |
19 | + * You should have received a copy of the GNU General Public License | |
20 | + * along with this program; if not, write to the Free Software | |
21 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
22 | + * MA 02110-1301 USA | |
23 | + */ | |
24 | + | |
25 | +#ifndef _PANTHEON_CONFIG_H | |
26 | +#define _PANTHEON_CONFIG_H | |
27 | + | |
28 | +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ | |
29 | + | |
30 | +#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ | |
31 | +#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ | |
32 | +#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ | |
33 | +#define MV_MFPR_BASE PANTHEON_MFPR_BASE | |
34 | +#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE | |
35 | +#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register | |
36 | + represents UART Unit Enable */ | |
37 | + | |
38 | +#endif /* _PANTHEON_CONFIG_H */ |
@@ -0,0 +1,79 @@ | ||
1 | +/* | |
2 | + * (C) Copyright 2011 | |
3 | + * Marvell Semiconductor <www.marvell.com> | |
4 | + * Written-by: Lei Wen <leiwen@marvell.com> | |
5 | + * | |
6 | + * See file CREDITS for list of people who contributed to this | |
7 | + * project. | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or | |
10 | + * modify it under the terms of the GNU General Public License as | |
11 | + * published by the Free Software Foundation; either version 2 of | |
12 | + * the License, or (at your option) any later version. | |
13 | + * | |
14 | + * This program is distributed in the hope that it will be useful, | |
15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | + * GNU General Public License for more details. | |
18 | + * | |
19 | + * You should have received a copy of the GNU General Public License | |
20 | + * along with this program; if not, write to the Free Software | |
21 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
22 | + * MA 02110-1301 USA | |
23 | + */ | |
24 | + | |
25 | +#ifndef _PANTHEON_CPU_H | |
26 | +#define _PANTHEON_CPU_H | |
27 | + | |
28 | +#include <asm/io.h> | |
29 | +#include <asm/system.h> | |
30 | + | |
31 | +/* | |
32 | + * Main Power Management (MPMU) Registers | |
33 | + * Refer Register Datasheet 9.1 | |
34 | + */ | |
35 | +struct panthmpmu_registers { | |
36 | + u8 pad0[0x0024]; | |
37 | + u32 ccgr; /*0x0024*/ | |
38 | + u8 pad1[0x0200 - 0x024 - 4]; | |
39 | + u32 wdtpcr; /*0x0200*/ | |
40 | + u8 pad2[0x1020 - 0x200 - 4]; | |
41 | + u32 aprr; /*0x1020*/ | |
42 | + u32 acgr; /*0x1024*/ | |
43 | +}; | |
44 | + | |
45 | +/* | |
46 | + * APB Clock Reset/Control Registers | |
47 | + * Refer Register Datasheet 6.14 | |
48 | + */ | |
49 | +struct panthapb_registers { | |
50 | + u32 uart0; /*0x000*/ | |
51 | + u32 uart1; /*0x004*/ | |
52 | + u32 gpio; /*0x008*/ | |
53 | + u8 pad0[0x034 - 0x08 - 4]; | |
54 | + u32 timers; /*0x034*/ | |
55 | +}; | |
56 | + | |
57 | +/* | |
58 | + * CPU Interface Registers | |
59 | + * Refer Register Datasheet 4.3 | |
60 | + */ | |
61 | +struct panthcpu_registers { | |
62 | + u32 chip_id; /* Chip Id Reg */ | |
63 | + u32 pad; | |
64 | + u32 cpu_conf; /* CPU Conf Reg */ | |
65 | + u32 pad1; | |
66 | + u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ | |
67 | + u32 pad2; | |
68 | + u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ | |
69 | + u32 mcb_conf; /* MCB Conf Reg */ | |
70 | + u32 sys_boot_ctl; /* Sytem Boot Control */ | |
71 | +}; | |
72 | + | |
73 | +/* | |
74 | + * Functions | |
75 | + */ | |
76 | +u32 panth_sdram_base(int); | |
77 | +u32 panth_sdram_size(int); | |
78 | + | |
79 | +#endif /* _PANTHEON_CPU_H */ |
@@ -0,0 +1,54 @@ | ||
1 | +/* | |
2 | + * (C) Copyright 2011 | |
3 | + * Marvell Semiconductor <www.marvell.com> | |
4 | + * Written-by: Lei Wen <leiwen@marvell.com> | |
5 | + * | |
6 | + * See file CREDITS for list of people who contributed to this | |
7 | + * project. | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or | |
10 | + * modify it under the terms of the GNU General Public License as | |
11 | + * published by the Free Software Foundation; either version 2 of | |
12 | + * the License, or (at your option) any later version. | |
13 | + * | |
14 | + * This program is distributed in the hope that it will be useful, | |
15 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | + * GNU General Public License for more details. | |
18 | + * | |
19 | + * You should have received a copy of the GNU General Public License | |
20 | + * along with this program; if not, write to the Free Software | |
21 | + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
22 | + * MA 02110-1301 USA | |
23 | + */ | |
24 | + | |
25 | +#ifndef _PANTHEON_H | |
26 | +#define _PANTHEON_H | |
27 | + | |
28 | +#ifndef __ASSEMBLY__ | |
29 | +#include <asm/types.h> | |
30 | +#include <asm/io.h> | |
31 | +#endif /* __ASSEMBLY__ */ | |
32 | + | |
33 | +#include <asm/arch/cpu.h> | |
34 | + | |
35 | +/* Common APB clock register bit definitions */ | |
36 | +#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ | |
37 | +#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ | |
38 | +#define APBC_RST (1<<2) /* Reset Generation */ | |
39 | +/* Functional Clock Selection Mask */ | |
40 | +#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) | |
41 | + | |
42 | +/* Register Base Addresses */ | |
43 | +#define PANTHEON_DRAM_BASE 0xB0000000 | |
44 | +#define PANTHEON_TIMER_BASE 0xD4014000 | |
45 | +#define PANTHEON_WD_TIMER_BASE 0xD4080000 | |
46 | +#define PANTHEON_APBC_BASE 0xD4015000 | |
47 | +#define PANTHEON_UART1_BASE 0xD4017000 | |
48 | +#define PANTHEON_UART2_BASE 0xD4018000 | |
49 | +#define PANTHEON_GPIO_BASE 0xD4019000 | |
50 | +#define PANTHEON_MFPR_BASE 0xD401E000 | |
51 | +#define PANTHEON_MPMU_BASE 0xD4050000 | |
52 | +#define PANTHEON_CPU_BASE 0xD4282C00 | |
53 | + | |
54 | +#endif /* _PANTHEON_H */ |