Revisión | 8c2fe29035f078836c51aa99106a0ec82190feb2 (tree) |
---|---|
Tiempo | 2019-06-13 12:26:16 |
Autor | Yoshinori Sato <ysato@user...> |
Commiter | Yoshinori Sato |
h8300 update
@@ -107,6 +107,7 @@ config ENV_VARS_UBOOT_CONFIG | ||
107 | 107 | |
108 | 108 | config NR_DRAM_BANKS |
109 | 109 | int "Number of DRAM banks" |
110 | + depends on !H8300 | |
110 | 111 | default 4 |
111 | 112 | help |
112 | 113 | This defines the number of DRAM banks. |
@@ -500,7 +501,7 @@ config SYS_EXTRA_OPTIONS | ||
500 | 501 | new boards should not use this option. |
501 | 502 | |
502 | 503 | config SYS_TEXT_BASE |
503 | - depends on !NIOS2 && !XTENSA | |
504 | + depends on !NIOS2 && !XTENSA && !H8300 | |
504 | 505 | depends on !EFI_APP |
505 | 506 | default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3 |
506 | 507 | default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S |
@@ -887,7 +887,7 @@ LDFLAGS_u-boot += $(LDFLAGS_FINAL) | ||
887 | 887 | # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards. |
888 | 888 | LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker) |
889 | 889 | |
890 | -ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),) | |
890 | +ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA)$(CONFIG_H8300),) | |
891 | 891 | LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) |
892 | 892 | endif |
893 | 893 |
@@ -3,7 +3,6 @@ config CREATE_ARCH_SYMLINK | ||
3 | 3 | |
4 | 4 | config HAVE_ARCH_IOREMAP |
5 | 5 | bool |
6 | - depends on HAVE_GENERIC_BOARD | |
7 | 6 | |
8 | 7 | choice |
9 | 8 | prompt "Architecture select" |
@@ -15,8 +14,6 @@ config ARC | ||
15 | 14 | select ARC_TIMER |
16 | 15 | select CLK |
17 | 16 | select HAVE_PRIVATE_LIBGCC |
18 | - select HAVE_GENERIC_BOARD | |
19 | - select SYS_GENERIC_BOARD | |
20 | 17 | select SUPPORT_OF_CONTROL |
21 | 18 | select TIMER |
22 | 19 |
@@ -26,14 +23,9 @@ config ARM | ||
26 | 23 | select HAVE_PRIVATE_LIBGCC if !ARM64 |
27 | 24 | select SUPPORT_OF_CONTROL |
28 | 25 | |
29 | -config AVR32 | |
30 | - bool "AVR32 architecture" | |
31 | - select HAVE_GENERIC_BOARD | |
32 | - | |
33 | -config BLACKFIN | |
34 | - bool "Blackfin architecture" | |
35 | - select HAVE_GENERIC_BOARD | |
36 | - select SYS_GENERIC_BOARD | |
26 | +config H8300 | |
27 | + bool "H8/300 architecture" | |
28 | + select SUPPORT_OF_CONTROL | |
37 | 29 | |
38 | 30 | config M68K |
39 | 31 | bool "M68000 architecture" |
@@ -44,8 +36,6 @@ config M68K | ||
44 | 36 | |
45 | 37 | config MICROBLAZE |
46 | 38 | bool "MicroBlaze architecture" |
47 | - select HAVE_GENERIC_BOARD | |
48 | - select SYS_GENERIC_BOARD | |
49 | 39 | select SUPPORT_OF_CONTROL |
50 | 40 | imply CMD_IRQ |
51 | 41 |
@@ -70,7 +60,6 @@ config NIOS2 | ||
70 | 60 | config PPC |
71 | 61 | bool "PowerPC architecture" |
72 | 62 | select HAVE_PRIVATE_LIBGCC |
73 | - select HAVE_GENERIC_BOARD | |
74 | 63 | select SUPPORT_OF_CONTROL |
75 | 64 | select SYS_BOOT_GET_CMDLINE |
76 | 65 | select SYS_BOOT_GET_KBD |
@@ -101,7 +90,6 @@ config SANDBOX | ||
101 | 90 | select DM_KEYBOARD |
102 | 91 | select DM_MMC |
103 | 92 | select DM_SERIAL |
104 | - select DM_I2C | |
105 | 93 | select DM_SPI |
106 | 94 | select DM_SPI_FLASH |
107 | 95 | select HAVE_BLOCK_DEVICE |
@@ -141,9 +129,6 @@ config SH | ||
141 | 129 | bool "SuperH architecture" |
142 | 130 | select HAVE_PRIVATE_LIBGCC |
143 | 131 | |
144 | -config SPARC | |
145 | - bool "SPARC architecture" | |
146 | - | |
147 | 132 | config X86 |
148 | 133 | bool "x86 architecture" |
149 | 134 | select SUPPORT_SPL |
@@ -291,19 +276,15 @@ config SYS_DISABLE_DCACHE_OPS | ||
291 | 276 | |
292 | 277 | source "arch/arc/Kconfig" |
293 | 278 | source "arch/arm/Kconfig" |
294 | -source "arch/avr32/Kconfig" | |
295 | -source "arch/blackfin/Kconfig" | |
296 | 279 | source "arch/h8300/Kconfig" |
297 | 280 | source "arch/m68k/Kconfig" |
298 | 281 | source "arch/microblaze/Kconfig" |
299 | 282 | source "arch/mips/Kconfig" |
300 | 283 | source "arch/nds32/Kconfig" |
301 | 284 | source "arch/nios2/Kconfig" |
302 | -source "arch/openrisc/Kconfig" | |
303 | 285 | source "arch/powerpc/Kconfig" |
304 | 286 | source "arch/sandbox/Kconfig" |
305 | 287 | source "arch/sh/Kconfig" |
306 | -source "arch/sparc/Kconfig" | |
307 | 288 | source "arch/x86/Kconfig" |
308 | 289 | source "arch/xtensa/Kconfig" |
309 | 290 | source "arch/riscv/Kconfig" |
@@ -41,6 +41,13 @@ config SYS_CPU | ||
41 | 41 | default "h8300h" if CPU_H8300H |
42 | 42 | default "h8300s" if CPU_H8S |
43 | 43 | |
44 | +config CPU_H83069 | |
45 | + bool | |
46 | + | |
47 | +config TIMER_BASE | |
48 | + hex | |
49 | + default 0xffff80 | |
50 | + | |
44 | 51 | source "board/h8300h_sim/Kconfig" |
45 | 52 | source "board/h8300s_sim/Kconfig" |
46 | 53 | source "board/ae3069/Kconfig" |
@@ -50,8 +50,9 @@ _start: | ||
50 | 50 | bne 1b |
51 | 51 | mov.l #_run_stack,sp |
52 | 52 | mov.l sp,er0 |
53 | - jsr @board_init_f_mem | |
53 | + jsr @board_init_f_alloc_reserve | |
54 | 54 | mov.l er0,sp |
55 | + jsr @board_init_f_init_reserve | |
55 | 56 | sub.l er0,er0 /* boot flags */ |
56 | 57 | jsr @board_init_f |
57 | 58 | bra . |
@@ -7,7 +7,7 @@ | ||
7 | 7 | interrupt-parent = <&h8intc>; |
8 | 8 | |
9 | 9 | chosen { |
10 | - stdout-path = &sci1; | |
10 | + stdout-path = &sci0; | |
11 | 11 | }; |
12 | 12 | aliases { |
13 | 13 | serial0 = &sci0; |
@@ -36,8 +36,7 @@ | ||
36 | 36 | clock-mult = <1>; |
37 | 37 | }; |
38 | 38 | |
39 | - memory@400000 { | |
40 | - device_type = "memory"; | |
39 | + memory { | |
41 | 40 | reg = <0x400000 0x400000>; |
42 | 41 | }; |
43 | 42 |
@@ -182,5 +182,7 @@ static __inline__ unsigned long __ffs(unsigned long word) | ||
182 | 182 | return result; |
183 | 183 | } |
184 | 184 | |
185 | +#include <asm-generic/bitops/fls.h> | |
186 | +#include <asm-generic/bitops/fls64.h> | |
185 | 187 | |
186 | 188 | #endif /* _H8300_BITOPS_H */ |
@@ -21,6 +21,4 @@ | ||
21 | 21 | #ifndef _ASM_CONFIG_H_ |
22 | 22 | #define _ASM_CONFIG_H_ |
23 | 23 | |
24 | -#define CONFIG_RELOC_FIXUP_WORKS | |
25 | - | |
26 | 24 | #endif |
@@ -0,0 +1,11 @@ | ||
1 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
2 | +/* | |
3 | + * U-Boot - linkage.h | |
4 | + * | |
5 | + * Copyright (c) 2005-2007 Analog Devices Inc. | |
6 | + */ | |
7 | + | |
8 | +#ifndef __ASM_LINKAGE_H | |
9 | +#define __ASM_LINKAGE_H | |
10 | + | |
11 | +#endif |
@@ -7,4 +7,4 @@ | ||
7 | 7 | # SPDX-License-Identifier: GPL-2.0+ |
8 | 8 | # |
9 | 9 | |
10 | -obj-y = bootm.o time.o gpio.o gd.o | |
10 | +obj-y = bootm.o gd.o time.o #gpio.o |
@@ -34,22 +34,15 @@ void n9604_udc_probe(void); | ||
34 | 34 | |
35 | 35 | int board_early_init_f(void) |
36 | 36 | { |
37 | +#if 0 | |
37 | 38 | h8300_gpio_init(); |
39 | +#endif | |
38 | 40 | #ifdef CONFIG_USB_GADGET_N9604 |
39 | 41 | n9604_udc_probe(); |
40 | 42 | #endif |
41 | 43 | return 0; |
42 | 44 | } |
43 | 45 | |
44 | -void dram_init_banksize(void) | |
45 | -{ | |
46 | - DECLARE_GLOBAL_DATA_PTR; | |
47 | - | |
48 | - gd->bd->bi_memstart = CONFIG_SYS_DRAM_BASE; | |
49 | - gd->bd->bi_memsize = CONFIG_SYS_DRAM_SIZE; | |
50 | - gd->ram_size = CONFIG_SYS_DRAM_SIZE; | |
51 | -} | |
52 | - | |
53 | 46 | #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) |
54 | 47 | int board_eth_init(bd_t *bis) |
55 | 48 | { |
@@ -66,9 +59,9 @@ int board_eth_init(bd_t *bis) | ||
66 | 59 | |
67 | 60 | int board_late_init(void) |
68 | 61 | { |
62 | +#ifdef CONFIG_CMD_MMC | |
69 | 63 | DECLARE_GLOBAL_DATA_PTR; |
70 | 64 | |
71 | -#ifdef CONFIG_CMD_MMC | |
72 | 65 | mmc_initialize(gd->bd); |
73 | 66 | #endif |
74 | 67 | #ifdef CONFIG_CMD_LED |
@@ -78,3 +71,16 @@ int board_late_init(void) | ||
78 | 71 | |
79 | 72 | return 0; |
80 | 73 | } |
74 | + | |
75 | +int dram_init(void) | |
76 | +{ | |
77 | + if (fdtdec_setup_mem_size_base() != 0) | |
78 | + return -EINVAL; | |
79 | + | |
80 | + return 0; | |
81 | +} | |
82 | + | |
83 | +int dram_init_banksize(void) | |
84 | +{ | |
85 | + return 0; | |
86 | +} |
@@ -455,6 +455,18 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | ||
455 | 455 | return 0; |
456 | 456 | } |
457 | 457 | |
458 | +#elif defined(CONFIG_H8300) | |
459 | + | |
460 | +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
461 | +{ | |
462 | + bd_t *bd = gd->bd; | |
463 | + | |
464 | + print_bi_mem(bd); | |
465 | + print_eth_ip_addr(); | |
466 | + print_baudrate(); | |
467 | + return 0; | |
468 | +} | |
469 | + | |
458 | 470 | #else |
459 | 471 | #error "a case for this architecture does not exist!" |
460 | 472 | #endif |
@@ -1,12 +0,0 @@ | ||
1 | -# | |
2 | -# (C) Copyright 2000-2006 | |
3 | -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | -# | |
5 | -# Copyright (C) 2014 Yoshinori Sato <ysato@users.sourceforge.jp> | |
6 | -# Copyright (C) 2008 Renesas Solutions Corp. | |
7 | -# | |
8 | -# SPDX-License-Identifier: GPL-2.0+ | |
9 | -# | |
10 | - | |
11 | -extra-y = start.o | |
12 | -obj-y = cpu.o interrupts.o watchdog.o |
@@ -1,27 +0,0 @@ | ||
1 | -# | |
2 | -# Copyright (C) 2010 Yoshinori Sato <ysato@users.sourceforge.jp> | |
3 | -# | |
4 | -# See file CREDITS for list of people who contributed to this | |
5 | -# project. | |
6 | -# | |
7 | -# This program is free software; you can redistribute it and/or | |
8 | -# modify it under the terms of the GNU General Public License as | |
9 | -# published by the Free Software Foundation; either version 2 of | |
10 | -# the License, or (at your option) any later version. | |
11 | -# | |
12 | -# This program is distributed in the hope that it will be useful, | |
13 | -# but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | -# GNU General Public License for more details. | |
16 | -# | |
17 | -# You should have received a copy of the GNU General Public License | |
18 | -# along with this program; if not, write to the Free Software | |
19 | -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | -# MA 02111-1307 USA | |
21 | -# | |
22 | -# | |
23 | -PLATFORM_CPPFLAGS += -mh -Wa,--mach=h8300h | |
24 | -CFLAGS += -mh | |
25 | -USE_PRIVATE_LIBGCC = $(shell dirname `$(CC) $(CFLAGS) -mh -print-libgcc-file-name`) | |
26 | -LDEMUL = -mh8300helf_linux | |
27 | -LDFLAGS += $(LDEMUL) |
@@ -1,84 +0,0 @@ | ||
1 | -/* | |
2 | - * Copyright (C) 2010 Yoshinori Sato <ysato@users.sourceforge.jp> | |
3 | - * | |
4 | - * See file CREDITS for list of people who contributed to this | |
5 | - * project. | |
6 | - * | |
7 | - * This program is free software; you can redistribute it and/or | |
8 | - * modify it under the terms of the GNU General Public License as | |
9 | - * published by the Free Software Foundation; either version 2 of | |
10 | - * the License, or (at your option) any later version. | |
11 | - * | |
12 | - * This program is distributed in the hope that it will be useful, | |
13 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | - * GNU General Public License for more details. | |
16 | - * | |
17 | - * You should have received a copy of the GNU General Public License | |
18 | - * along with this program; if not, write to the Free Software | |
19 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | - * MA 02111-1307 USA | |
21 | - */ | |
22 | - | |
23 | -#include <common.h> | |
24 | -#include <command.h> | |
25 | -#include <asm/processor.h> | |
26 | -#include <asm/io.h> | |
27 | - | |
28 | -int checkcpu(void) | |
29 | -{ | |
30 | - puts("CPU: H8/300H\n"); | |
31 | - return 0; | |
32 | -} | |
33 | - | |
34 | -int arch_cpu_init(void) | |
35 | -{ | |
36 | - DECLARE_GLOBAL_DATA_PTR; | |
37 | - gd->ram_size = CONFIG_SYS_DRAM_SIZE; | |
38 | - gd->cpu_clk = CONFIG_SYS_CLK_FREQ; | |
39 | - return 0; | |
40 | -} | |
41 | - | |
42 | -int cleanup_before_linux(void) | |
43 | -{ | |
44 | - disable_interrupts(); | |
45 | - return 0; | |
46 | -} | |
47 | - | |
48 | -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
49 | -{ | |
50 | - disable_interrupts(); | |
51 | - reset_cpu(0); | |
52 | - return 0; | |
53 | -} | |
54 | - | |
55 | -void flush_cache(unsigned long addr, unsigned long size) | |
56 | -{ | |
57 | - | |
58 | -} | |
59 | - | |
60 | -void icache_enable(void) | |
61 | -{ | |
62 | -} | |
63 | - | |
64 | -void icache_disable(void) | |
65 | -{ | |
66 | -} | |
67 | - | |
68 | -int icache_status(void) | |
69 | -{ | |
70 | - return 0; | |
71 | -} | |
72 | - | |
73 | -void dcache_enable(void) | |
74 | -{ | |
75 | -} | |
76 | - | |
77 | -void dcache_disable(void) | |
78 | -{ | |
79 | -} | |
80 | - | |
81 | -int dcache_status(void) | |
82 | -{ | |
83 | - return 0; | |
84 | -} |
@@ -1,38 +0,0 @@ | ||
1 | -/* | |
2 | - * Copyright 2010 Yoshinori Sato <ysato@users.sourceforge.jp> | |
3 | - * | |
4 | - * See file CREDITS for list of people who contributed to this | |
5 | - * project. | |
6 | - * | |
7 | - * This program is free software; you can redistribute it and/or | |
8 | - * modify it under the terms of the GNU General Public License as | |
9 | - * published by the Free Software Foundation; either version 2 of | |
10 | - * the License, or (at your option) any later version. | |
11 | - * | |
12 | - * This program is distributed in the hope that it will be useful, | |
13 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | - * GNU General Public License for more details. | |
16 | - * | |
17 | - * You should have received a copy of the GNU General Public License | |
18 | - * along with this program; if not, write to the Free Software | |
19 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | - * MA 02111-1307 USA | |
21 | - */ | |
22 | - | |
23 | -#include <common.h> | |
24 | - | |
25 | -int interrupt_init(void) | |
26 | -{ | |
27 | - return 0; | |
28 | -} | |
29 | - | |
30 | -void enable_interrupts(void) | |
31 | -{ | |
32 | - | |
33 | -} | |
34 | - | |
35 | -int disable_interrupts(void) | |
36 | -{ | |
37 | - return 0; | |
38 | -} |
@@ -1,65 +0,0 @@ | ||
1 | -/* | |
2 | - * Copyright (C) 2010 Yoshinori Sato <ysato@users.sourceforge.jp> | |
3 | - | |
4 | - * This program is free software; you can redistribute it and/or | |
5 | - * modify it under the terms of the GNU General Public License as | |
6 | - * published by the Free Software Foundation; either version 2 of | |
7 | - * the License, or (at your option) any later version. | |
8 | - * | |
9 | - * This program is distributed in the hope that it will be useful, | |
10 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | - * GNU General Public License for more details. | |
13 | - * | |
14 | - * You should have received a copy of the GNU General Public License | |
15 | - * along with this program; if not, write to the Free Software | |
16 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | - * MA 02111-1307 USA | |
18 | - */ | |
19 | - | |
20 | -#include <config.h> | |
21 | -#include <version.h> | |
22 | - | |
23 | - .h8300h | |
24 | - | |
25 | - .section ".vector","ax" | |
26 | - .global _start | |
27 | - .global relocate_code | |
28 | - .long _start | |
29 | -vector = 1 | |
30 | - .rept 63 | |
31 | - .long __ram_vec + (vector * 4) | |
32 | -vector = vector + 1 | |
33 | - .endr | |
34 | - | |
35 | - .text | |
36 | - .align 2 | |
37 | -_start: | |
38 | - mov.l #__init_stack,sp | |
39 | - jsr @_lowlevel_init | |
40 | - | |
41 | - mov.l #__bss_start,er4 | |
42 | - mov.l #__bss_end,er5 | |
43 | - sub er4,er5 | |
44 | - shlr.l er5 | |
45 | - shlr.l er5 | |
46 | - sub.l er0,er0 | |
47 | -1: mov.l er0,@er4 /* bss clear */ | |
48 | - adds #4,er4 | |
49 | - dec.l #1,er5 | |
50 | - bne 1b | |
51 | - | |
52 | - mov.l #_run_stack,sp | |
53 | - mov.l sp,er0 | |
54 | - jsr @board_init_f_mem | |
55 | - mov.l er0,sp | |
56 | - sub.l er0,er0 /* boot flags */ | |
57 | - jsr @board_init_f | |
58 | - bra . | |
59 | - | |
60 | -relocate_code: | |
61 | - mov.l er1,er0 | |
62 | - sub.l er1,er1 | |
63 | - jmp @board_init_r | |
64 | - | |
65 | - .end |
@@ -1,32 +0,0 @@ | ||
1 | -/* | |
2 | - * Copyright (C) 2010 Yoshinori Sato <ysato@users.sourceforge.jp> | |
3 | - * | |
4 | - * This program is free software; you can redistribute it and/or | |
5 | - * modify it under the terms of the GNU General Public License as | |
6 | - * published by the Free Software Foundation; either version 2 of | |
7 | - * the License, or (at your option) any later version. | |
8 | - * | |
9 | - * This program is distributed in the hope that it will be useful, | |
10 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | - * GNU General Public License for more details. | |
13 | - * | |
14 | - * You should have received a copy of the GNU General Public License | |
15 | - * along with this program; if not, write to the Free Software | |
16 | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | - * MA 02111-1307 USA | |
18 | - */ | |
19 | - | |
20 | -#include <common.h> | |
21 | -#include <asm/processor.h> | |
22 | - | |
23 | -int watchdog_init(void) | |
24 | -{ | |
25 | - return 0; | |
26 | -} | |
27 | - | |
28 | -void reset_cpu(unsigned long ignored) | |
29 | -{ | |
30 | - while (1) | |
31 | - ; | |
32 | -} |
@@ -294,7 +294,7 @@ static void *alloc_priv(int size, uint flags) | ||
294 | 294 | * TODO(sjg@chromium.org): Drop this microblaze |
295 | 295 | * exception. |
296 | 296 | */ |
297 | -#ifndef CONFIG_MICROBLAZE | |
297 | +#if !defined(CONFIG_MICROBLAZE) && !defined(CONFIG_H8300) | |
298 | 298 | flush_dcache_range((ulong)priv, (ulong)priv + size); |
299 | 299 | #endif |
300 | 300 | } |
@@ -645,19 +645,6 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, | ||
645 | 645 | return ret; |
646 | 646 | } |
647 | 647 | |
648 | -static struct mxc_i2c_bus mxc_i2c_buses[] = { | |
649 | - | |
650 | - ret = i2c_init_transfer(i2c_bus, chip, addr, alen); | |
651 | - if (ret < 0) | |
652 | - return ret; | |
653 | - | |
654 | - ret = i2c_write_data(i2c_bus, chip, buf, len); | |
655 | - | |
656 | - i2c_imx_stop(i2c_bus); | |
657 | - | |
658 | - return ret; | |
659 | -} | |
660 | - | |
661 | 648 | #if !defined(I2C2_BASE_ADDR) |
662 | 649 | #define I2C2_BASE_ADDR 0 |
663 | 650 | #endif |
@@ -656,7 +656,7 @@ config SANDBOX_SERIAL | ||
656 | 656 | |
657 | 657 | config SCIF_CONSOLE |
658 | 658 | bool "Renesas SCIF UART support" |
659 | - depends on SH || ARCH_RMOBILE | |
659 | + depends on SH || ARCH_RMOBILE || H8300 | |
660 | 660 | help |
661 | 661 | Select this to enable Renesas SCIF UART. To operate serial ports |
662 | 662 | on systems with RCar or SH SoCs, say Y to this option. If unsure, |
@@ -36,7 +36,7 @@ static int scif_rxfill(struct uart_port *port) | ||
36 | 36 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; |
37 | 37 | } |
38 | 38 | } |
39 | -#elif defined(CONFIG_SCI) | |
39 | +#elif defined(CONFIG_H8300) | |
40 | 40 | static int scif_rxfill(struct uart_port *port) |
41 | 41 | { |
42 | 42 | return (sci_in(port, SCxSR) & SCxSR_RDxF(port))?1:0; |
@@ -56,20 +56,6 @@ struct uart_port { | ||
56 | 56 | # define SCSPTR5 0xFFE45020 |
57 | 57 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
58 | 58 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
59 | -#elif defined(CONFIG_CPU_H83007) || \ | |
60 | - defined(CONFIG_CPU_H83068) || \ | |
61 | - defined(CONFIG_CPU_H83069) | |
62 | -# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
63 | -# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) | |
64 | -# define SCIF0_BASE 0xffffb0 | |
65 | -# define SCIF1_BASE 0xffffb8 | |
66 | -# define SCIF2_BASE 0xffffc0 | |
67 | -#elif defined(CONFIG_CPU_H8S2678) | |
68 | -# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
69 | -# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) | |
70 | -# define SCIF0_BASE 0xffff78 | |
71 | -# define SCIF1_BASE 0xffff80 | |
72 | -# define SCIF2_BASE 0xffff88 | |
73 | 59 | #elif defined(CONFIG_CPU_SH7757) || \ |
74 | 60 | defined(CONFIG_CPU_SH7752) || \ |
75 | 61 | defined(CONFIG_CPU_SH7753) |
@@ -113,6 +99,8 @@ struct uart_port { | ||
113 | 99 | # endif |
114 | 100 | # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) |
115 | 101 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ |
102 | +#elif defined(CONFIG_H8300) | |
103 | +# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
116 | 104 | #else |
117 | 105 | # error CPU subtype not defined |
118 | 106 | #endif |
@@ -183,6 +171,10 @@ struct uart_port { | ||
183 | 171 | # else |
184 | 172 | # define SCIF_RFDC_MASK 0x001f |
185 | 173 | # endif |
174 | +#elif defined(CONFIG_H8300) | |
175 | +# define SCIF_ERRORS (SCI_ORER | SCI_FER | SCI_PER) | |
176 | +# define SCIF_RFDC_MASK 0x00 | |
177 | +# define SCIF_TXROOM_MAX 1 | |
186 | 178 | #else |
187 | 179 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
188 | 180 | # define SCIF_RFDC_MASK 0x001f |
@@ -194,7 +186,7 @@ struct uart_port { | ||
194 | 186 | #endif |
195 | 187 | |
196 | 188 | #define SCxSR_TEND(port)\ |
197 | - (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TEND) | |
189 | + (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | |
198 | 190 | #define SCxSR_ERRORS(port)\ |
199 | 191 | (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) |
200 | 192 | #define SCxSR_RDxF(port)\ |
@@ -274,16 +266,6 @@ static inline void sci_##name##_out(struct uart_port *port,\ | ||
274 | 266 | }\ |
275 | 267 | } |
276 | 268 | |
277 | -#if defiend(CONFIG_H8300) | |
278 | -/* h8300 don't have SCIF */ | |
279 | -#define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
280 | - static inline unsigned int sci_##name##_in(struct uart_port *port) {\ | |
281 | - return 0;\ | |
282 | - }\ | |
283 | - static inline void sci_##name##_out(struct uart_port *port,\ | |
284 | - unsigned int value) {\ | |
285 | - } | |
286 | -#else | |
287 | 269 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ |
288 | 270 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ |
289 | 271 | SCI_IN(scif_size, scif_offset);\ |
@@ -327,6 +309,13 @@ static inline void sci_##name##_out(struct uart_port *port,\ | ||
327 | 309 | sh4_scif_offset, sh4_scif_size) \ |
328 | 310 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) |
329 | 311 | #endif |
312 | +#elif defined(CONFIG_CPU_SH7723) | |
313 | + #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ | |
314 | + sh4_scif_offset, sh4_scif_size) \ | |
315 | + CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ | |
316 | + sh4_scif_offset, sh4_scif_size) | |
317 | + #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | |
318 | + CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
330 | 319 | #elif defined(CONFIG_H8300) || defined(CONFIG_RX) |
331 | 320 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ |
332 | 321 | sh4_sci_offset, sh4_sci_size, \ |
@@ -334,16 +323,9 @@ static inline void sci_##name##_out(struct uart_port *port,\ | ||
334 | 323 | sh4_scif_offset, sh4_scif_size, \ |
335 | 324 | h8_sci_offset, h8_sci_size) \ |
336 | 325 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) |
337 | -#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ | |
326 | +#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ | |
338 | 327 | sh4_scif_offset, sh4_scif_size) \ |
339 | 328 | CPU_SCIF_FNS(name, 0, 0) |
340 | -#elif defined(CONFIG_CPU_SH7723) | |
341 | - #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ | |
342 | - sh4_scif_offset, sh4_scif_size) \ | |
343 | - CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ | |
344 | - sh4_scif_offset, sh4_scif_size) | |
345 | - #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | |
346 | - CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
347 | 329 | #else |
348 | 330 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ |
349 | 331 | sh4_sci_offset, sh4_sci_size, \ |
@@ -458,59 +440,7 @@ SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ | ||
458 | 440 | #define sci_in(port, reg) sci_##reg##_in(port) |
459 | 441 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) |
460 | 442 | |
461 | -/* H8/300 series SCI pins assignment */ | |
462 | -#if defined(CONFIG_H8300) | |
463 | -static const struct __attribute__((packed)) { | |
464 | - int port; /* GPIO port no */ | |
465 | - unsigned short rx, tx; /* GPIO bit no */ | |
466 | -} h8300_sci_pins[] = { | |
467 | -#if defined(CONFIG_CPU_H83007) || defined(CONFIG_CPU_H83068) | |
468 | - { /* SCI0 */ | |
469 | - .port = H8300_GPIO_P9, | |
470 | - .rx = H8300_GPIO_B2, | |
471 | - .tx = H8300_GPIO_B0, | |
472 | - }, | |
473 | - { /* SCI1 */ | |
474 | - .port = H8300_GPIO_P9, | |
475 | - .rx = H8300_GPIO_B3, | |
476 | - .tx = H8300_GPIO_B1, | |
477 | - }, | |
478 | - { /* SCI2 */ | |
479 | - .port = H8300_GPIO_PB, | |
480 | - .rx = H8300_GPIO_B7, | |
481 | - .tx = H8300_GPIO_B6, | |
482 | - } | |
483 | -#elif defined(CONFIG_H8S2678) | |
484 | - { /* SCI0 */ | |
485 | - .port = H8300_GPIO_P3, | |
486 | - .rx = H8300_GPIO_B2, | |
487 | - .tx = H8300_GPIO_B0, | |
488 | - }, | |
489 | - { /* SCI1 */ | |
490 | - .port = H8300_GPIO_P3, | |
491 | - .rx = H8300_GPIO_B3, | |
492 | - .tx = H8300_GPIO_B1, | |
493 | - }, | |
494 | - { /* SCI2 */ | |
495 | - .port = H8300_GPIO_P5, | |
496 | - .rx = H8300_GPIO_B1, | |
497 | - .tx = H8300_GPIO_B0, | |
498 | - } | |
499 | -#endif | |
500 | -}; | |
501 | -#endif | |
502 | - | |
503 | -#if defined(CONFIG_CPU_SH7706) || \ | |
504 | - defined(CONFIG_CPU_SH7707) || \ | |
505 | - defined(CONFIG_CPU_SH7708) || \ | |
506 | - defined(CONFIG_CPU_SH7709) | |
507 | -static inline int sci_rxd_in(struct uart_port *port) | |
508 | -{ | |
509 | - if (port->mapbase == 0xfffffe80) | |
510 | - return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
511 | - return 1; | |
512 | -} | |
513 | -#elif defined(CONFIG_CPU_SH7750) || \ | |
443 | +#if defined(CONFIG_CPU_SH7750) || \ | |
514 | 444 | defined(CONFIG_CPU_SH7751) || \ |
515 | 445 | defined(CONFIG_CPU_SH7751R) || \ |
516 | 446 | defined(CONFIG_CPU_SH7750R) || \ |
@@ -521,11 +451,6 @@ static inline int sci_rxd_in(struct uart_port *port) | ||
521 | 451 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ |
522 | 452 | return 1; |
523 | 453 | } |
524 | -#elif defined(CONFIG_H8300) | |
525 | -static inline int sci_rxd_in(struct uart_port *port) | |
526 | -{ | |
527 | - return 1; | |
528 | -} | |
529 | 454 | #else /* default case for non-SCI processors */ |
530 | 455 | static inline int sci_rxd_in(struct uart_port *port) |
531 | 456 | { |
@@ -25,15 +25,10 @@ | ||
25 | 25 | #ifndef __KANEBEBE_H |
26 | 26 | #define __KANEBEBE_H |
27 | 27 | |
28 | -#define CONFIG_CPU_H83069 1 | |
29 | -#define CONFIG_H8300_RELOCATE 0 | |
30 | - | |
31 | 28 | /*#define CONFIG_SYS_LDSCRIPT "board/nisshin-tech/kanebebe/u-boot.lds.ram"*/ |
32 | 29 | |
33 | -#define CONFIG_BAUDRATE 38400 | |
34 | 30 | #define CONFIG_BOOTARGS "earlyprintk=sh-sci.1,38400 console=ttySC1,38400" |
35 | 31 | #define CONFIG_BOARD_LATE_INIT |
36 | -#define CONFIG_SYS_TEXT_BASE 0x008000 | |
37 | 32 | #define CONFIG_SYS_MONITOR_BASE 0x7b0000 |
38 | 33 | #define CONFIG_BOARD_EARLY_INIT_F |
39 | 34 | #undef CONFIG_VERSION_VARIABLE |
@@ -42,7 +37,6 @@ | ||
42 | 37 | /* MEMORY */ |
43 | 38 | #define KANEBEBE_DRAM_BASE 0x400000 |
44 | 39 | |
45 | -#define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
46 | 40 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
47 | 41 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
48 | 42 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
@@ -52,17 +46,12 @@ | ||
52 | 46 | /* List of legal baudrate settings for this board */ |
53 | 47 | #define CONFIG_SYS_BAUDRATE_TABLE { 38400 } |
54 | 48 | #define CONFIG_DOS_PARTITION |
55 | -#define CONFIG_OF_LIBFDT | |
56 | 49 | #define CONFIG_LMB |
57 | 50 | |
58 | 51 | /* SCI */ |
59 | -#define CONFIG_SCI 1 | |
60 | 52 | #define CONFIG_SCIF_CONSOLE 1 |
61 | 53 | #define CONFIG_CONS_SCIF1 1 |
62 | 54 | |
63 | -/* TIMER */ | |
64 | -#define CONFIG_TIMER_BASE 0xffff80 /* CH0-1 */ | |
65 | - | |
66 | 55 | #define CONFIG_SYS_MEMTEST_START KANEBEBE_DRAM_BASE |
67 | 56 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024)) |
68 | 57 |
@@ -86,19 +75,12 @@ | ||
86 | 75 | |
87 | 76 | #define CONFIG_SYS_RX_ETH_BUFFER 1 |
88 | 77 | |
89 | -#define CONFIG_SYS_NO_FLASH 1 | |
90 | 78 | /*#define CONFIG_HAS_DATAFLASH 1*/ |
91 | 79 | |
92 | 80 | /* Board Clock */ |
93 | 81 | #define CONFIG_SYS_CLK_FREQ 25000000 |
94 | 82 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
95 | 83 | |
96 | -/* GPIO */ | |
97 | -#define CONFIG_H8300_GPIO \ | |
98 | - {0x00,0x00,0x00,0x00,0xff,0x0f,0x87,0xff,0x00,0xff,0xef} | |
99 | -#define CONFIG_H8300_INIT_DDR \ | |
100 | - {0xff,0xff,0x00,0x00,0x01,0x00,0x00,0x0e,0x00,0xff,0x00} | |
101 | - | |
102 | 84 | #ifdef CONFIG_NET |
103 | 85 | #define CONFIG_DRIVER_NE2000 1 |
104 | 86 | #define CONFIG_DRIVER_NE2000_BASE 0x200000 |
@@ -195,7 +195,7 @@ enum { | ||
195 | 195 | IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ |
196 | 196 | IH_ARCH_XTENSA, /* Xtensa */ |
197 | 197 | IH_ARCH_RISCV, /* RISC-V */ |
198 | - | |
198 | + IH_ARCH_H8300, /* H8/300 */ | |
199 | 199 | IH_ARCH_COUNT, |
200 | 200 | }; |
201 | 201 |