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CI: Add Aspeed AST2600

The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.

Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>

aspeed/spl: Remove OVERLAY from linker script

The generic arm linker script contains this section:

.bss __rel_dyn_start (OVERLAY) : {
...
}

The (OVERLAY) syntax in the description causes the .bss section to be
included in the NOR area of the image:

$ objdump -t -j .bss spl/u-boot-spl
SYMBOL TABLE:
0000c61c l d .bss 00000000 .bss
0000c640 l O .bss 00000040 __value.0
0000c68c g O .bss 00000000 __bss_end
0000c61c g O .bss 00000000 __bss_start
0000c680 g O .bss 0000000c stdio_devices

This is what the custom linker script tries to avoid, as the NOR area is
read-only.

Remove the OVERLAY syntax to fix the BSS location:

$ objdump -t -j .bss spl/u-boot-spl
SYMBOL TABLE:
83000000 l d .bss 00000000 .bss
83000000 l O .bss 00000040 __value.0
0000c61c g O .bss 00000000 __image_copy_end
8300004c g O .bss 00000000 __bss_end
83000000 g O .bss 00000000 __bss_start
83000040 g O .bss 0000000c stdio_devices

This restores the state of the linker script before the patch that fixed
the linker lists issue.

Fixes: f6810b749f2e ("aspeed/ast2600: Fix SPL linker script")
Signed-off-by: Joel Stanley <joel@jms.id.au>

ast2600: Configure u-boot-with-spl.bin target

The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.

The u-boot-with-spl.bin target will add padding according to
CONFIG_SPL_MAX_SIZE which defaults to 64KB on the AST2600.

With this the following simple steps can be used to build and boot a
system:

make u-boot-with-spl.bin
truncate -s 64M u-boot-with-spl.bin
qemu-system-arm -nographic -M ast2600-evb \
-drive file=u-boot-with-spl.bin,if=mtd,format=raw

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

spl: Set SPL_MAX_SIZE default for AST2600

The AST2600 bootrom has a max size of 64KB. This can be overridden if the
system is running the SPL from SPI NOR and not using secure boot.

Signed-off-by: Joel Stanley <joel@jms.id.au>

config/ast2600: Disable hash hardware accel

The HACE driver lacks support for all the hash types, causing boot to
fail with the default FIT configuration which uses CRC32.

Additionally the Qemu model or the u-boot driver is unable to correctly
compute the SHA256 hash used in a FIT.

Disable HACE by default while the above issues are worked out to enable
boot testing in Qemu.

Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>

config/ast2600: Make position independent

Allows loading one u-boot from another. Useful for testing on hardware.

Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>

config/ast2600: Enable CRC32

Useful for testing images with the default hash type.

Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>

config/ast2600: Enable eMMC related boot options

Allow booting zImage from ext4 devices with DOS or UEFI partition
layouts.

Signed-off-by: Joel Stanley <joel@jms.id.au>

mmc/aspeed: Enable controller clocks

Request and enable the controller level clocks.

Signed-off-by: Joel Stanley <joel@jms.id.au>

mmc/aspeed: Probe from controller

The Aspeed SDHCI controller is arranged with some shared control
registers, followed by one or two sets of actual SDHCI registers.

Adjust the driver to probe this controller device first. The driver then
wants to iterate over the child nodes to probe the SDHCI proper:

ofnode node;

dev_for_each_subnode(node, parent) {
struct udevice *dev;
int ret;

ret = device_bind_driver_to_node(parent, "aspeed_sdhci",
ofnode_get_name(node),
node, &dev);
if (ret)
return ret;
}

However if we did this the sdhci driver would probe twice; once
"naturally" from the device tree and a second time due to this code.

Instead of doing this we can rely on the probe order, where the
controller will be set up before the sdhci devices. A better solution is
preferred.

Select MISC as the controller driver is implemented as a misc device.

Signed-off-by: Joel Stanley <joel@jms.id.au>

mmc/aspeed: Add debuging for clock probe failures

Signed-off-by: Joel Stanley <joel@jms.id.au>

clk/ast2500: Add SD clock

In order to use the clock from the sdhci driver, add the SD clock.

Signed-off-by: Joel Stanley <joel@jms.id.au>

clk/ast2600: Adjust eMMC clock names

Adjust clock to stay compatible with those used by the Linux kernel
device tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>

clk/aspeed: Add debug message when clock fails

A common message across platforms that prints the clock number.

Signed-off-by: Joel Stanley <joel@jms.id.au>

ARM: dts: ast2500: Update SDHCI nodes

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley <joel@jms.id.au>

ARM: dts: ast2600: Update SDHCI nodes

Match the description used by the Linux kernel, except use scu instead
of syscon as the phandle.

Signed-off-by: Joel Stanley <joel@jms.id.au>

config/aspeed: Enable EEPROM options

To allow testing of the I2C driver, enable the eprom command and the
misc driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>

config/ast2600: Enable I2C driver

Signed-off-by: Joel Stanley <joel@jms.id.au>

i2c/aspeed: Add AST2600 compatible

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

i2c/aspeed: Fix reset control

The reset control was written for the ast2500 and directly programs the
clocking register.

So we can share the code with other SoC generations use the reset device
to deassert the I2C reset line.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

reset/aspeed: Implement status callback

The I2C driver shares a reset line between buses, so allow it to test
the state of the reset line before resetting it.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

ARM: dts: ast2600-evb: Add I2C devices

The EVB has an EEPROM and ADT8490 temp sensor/fan controller on bus 7,
and a LM75 temp sensor on bus 8.

Signed-off-by: Joel Stanley <joel@jms.id.au>

ARM: dts: ast2500-evb: Add I2C devices

The EVB has an EEPROM on bus 3 and a LM75 temp sensor on bus 7. Enable
those busses we can test the I2C driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

ARM: dts: ast2600-evb: Remove redundant pinctrl

Now that these are in the dtsi we don't need them in the EVB device
tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>

ARM: dts: ast2600: Disable I2C nodes by default

Allow boards to enable the buses they use.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

ARM: dts: ast2600: Add I2C reset properties

The same as the upstream Linux device tree, each i2c bus has a property
specifying the reset line.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>

ARM: dts: ast2600: Add I2C pinctrl

Set the pinctrl groups for each I2C bus. These are essential to
I2C operating correctly.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

soc: soc_ti_k3: identify j7200 SR2.0 SoCs

Anytime a new revision of a chip is produced, Texas Instruments
will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID
register by one. Typically this will be decoded as SR1.0 -> SR2.0 ...
however a few TI SoCs do not follow this convention.

Rather than defining a revision string array for each SoC, use a
default revision string array for all TI SoCs that continue to follow
the typical 1.0 -> 2.0 revision scheme.

Signed-off-by: Bryan Brattlof <bb@ti.com>

phy: nuvoton: add NPCM7xx phy control driver

add BMC NPCM750 phy control driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>

toradex: tdx-cfg-block: add new toradex oui range

Add new Toradex MAC OUI (8c:06:cb), to the config block. With this change
we extend the possible serial-numbers as follows:

For serial-numbers 00000000-16777215 OUI 00:14:2d is taken
For serial-numbers 16777216-33554431 OUI 8c:06:cb is taken

Lower 24-bit of the serial number are used in the NIC part of the
MAC address, the complete serial number can be calculated using the OUI.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>